EnergyConverter.vhd

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library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
 
library work;
use work.DataTypes.all;
use work.AlgoDataTypes.all;
 
entity EnergyConverter is
  generic(
    ENCODING_MODE : integer
    );
  port (
    clk          : in  std_logic;
    is_hadronic  : in  std_logic := '0';
    IN_threshold : in  std_logic_vector(INPUT_DATA_WIDTH-1 downto 0);
    IN_Load      : in  std_logic;
    IN_Data      : in  std_logic_vector(INPUT_DATA_WIDTH-1 downto 0);
    OUT_Data     : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
end entity EnergyConverter;
 
 
architecture str of EnergyConverter is
  -----------------------------------------------------------------------------
  -- Internal signal declarations
  -----------------------------------------------------------------------------
  signal Data : std_logic_vector(INPUT_DATA_WIDTH-1 downto 0);
 
  signal IntegerOutData0 : unsigned(DATA_WIDTH-7 downto 0);
  signal IntegerOutData1 : unsigned(DATA_WIDTH-6 downto 0);
  signal IntegerOutData2 : unsigned(DATA_WIDTH-5 downto 0);
  signal IntegerOutData3 : unsigned(DATA_WIDTH-4 downto 0);
  signal IntegerOutData4 : unsigned(DATA_WIDTH-3 downto 0);
  signal OverThreshold   : std_logic;
  signal Data2, Data4    : std_logic_vector(DATA_WIDTH-1 downto 0);
  signal Saturated       : std_logic;
  signal Invalid         : std_logic;
  signal Negative        : std_logic;
 
  signal OutData : std_logic_vector(DATA_WIDTH-1 downto 0);
  signal special : std_logic_vector(1 downto 0);
 
begin  -- architecture str
  -----------------------------------------------------------------------------
  -- Component instantiations
  -----------------------------------------------------------------------------
 
  ENCODING_IF : if ENCODING_MODE = 1 generate
 
    Sync_proc : process (clk)
    begin
      if rising_edge(clk) then
        if IN_Load = '1' then
          Data          <= IN_Data;
          OverThreshold <= '0' when unsigned(IN_Data) <= unsigned(IN_threshold)                           else '1';
          Invalid       <= '1' when IN_Data = "1111111110" or IN_Data = "1111111101"                      else '0';
          Saturated     <= '1' when unsigned(IN_Data) > 1011                                              else '0';
          Negative      <= '1' when IN_Data(INPUT_DATA_WIDTH -1 downto 5) = "00000" and is_hadronic = '0' else '0';
          Data2         <= '0'&'0'&'0'&'0'& IN_Data &'0'&'0';
          Data4         <= '0'&'0'& IN_Data &'0'&'0'&'0'&'0';
 
          IntegerOutData0 <= unsigned(IN_Data) - 32;
          IntegerOutData1 <= unsigned(IN_Data &'0') - 128;
          IntegerOutData2 <= unsigned(IN_Data &'0'&'0') - 512;
          IntegerOutData3 <= unsigned(IN_Data &'0'&'0'&'0') - 2048;
          IntegerOutData4 <= unsigned(IN_Data &'0'&'0'&'0'&'0') - 8192;
        else
          Data          <= Data;
          OverThreshold <= OverThreshold;
          Invalid       <= Invalid;
          Saturated     <= Saturated;
          Data2         <= Data2;
          Data4         <= Data4;
 
          IntegerOutData0 <= IntegerOutData0;
          IntegerOutData1 <= IntegerOutData1;
          IntegerOutData2 <= IntegerOutData2;
          IntegerOutData3 <= IntegerOutData3;
          IntegerOutData4 <= IntegerOutData4;
 
        end if;
 
        OUT_Data <= "0000000000000000" when OverThreshold = '0' or Invalid = '1' or Negative = '1' else
                    "1111111111111111"                                                          when Saturated = '1' else
                    std_logic_vector(unsigned(Data2) + unsigned(Data4))                         when is_hadronic = '1' else
                    (DATA_WIDTH-3 downto 0 => std_logic_vector(IntegerOutData4), others => '0') when unsigned(Data) > 767 else
                    (DATA_WIDTH-4 downto 0 => std_logic_vector(IntegerOutData3), others => '0') when unsigned(Data) > 383 else
                    (DATA_WIDTH-5 downto 0 => std_logic_vector(IntegerOutData2), others => '0') when unsigned(Data) > 191 else
                    (DATA_WIDTH-6 downto 0 => std_logic_vector(IntegerOutData1), others => '0') when unsigned(Data) > 95 else
                    (DATA_WIDTH-7 downto 0 => std_logic_vector(IntegerOutData0), others => '0');
 
      end if;
    end process Sync_proc;
 
  elsif ENCODING_MODE = 2       -- Steve'scheme
    generate
 
    data_proc : process (clk)
    begin
      if rising_edge(clk) then
        if IN_Load = '1' then
          if is_hadronic = '1' then
            OutData <= '0'& std_logic_vector(unsigned('0' & IN_Data & '0'&'0'&'0'&'0') + unsigned('0'& IN_Data &'0'&'0'));
          else
            case IN_Data(9 downto 8) is
              when "00" =>
                if IN_Data(7 downto 5) = "000" then
                  OutData <= "0000000000000000";
                else
                  OutData <= '0'&'0'&'0'&'0'&'0'&'0'&'0'&'0'&std_logic_vector(unsigned(IN_Data(7 downto 0)) - 32);  --8 bit
                end if;
              when "01" =>
                OutData <= '0'&'0'&'0'&'0'&'0'&'0'&std_logic_vector(unsigned('0'&IN_Data(7 downto 0)&'0') + 224);   --9 bit
              when "10" =>
                OutData <= '0'&'0'&'0'&'0'&'0'&std_logic_vector(unsigned('0'&IN_Data(7 downto 0)&'0'&'0') + 736);   --11 bit
              when others =>
                OutData <= '0'&'0'&'0'&std_logic_vector(unsigned('0'&IN_Data(7 downto 0)&'0'&'0'&'0'&'0') + 1760);  --12 bit
            end case;
          end if;
        else
          OutData <= OutData;
        end if;
      end if;
    end process data_proc;
 
    special_proc : process (clk)
    begin
      if rising_edge(clk) then
        if IN_Load = '1' then
          if unsigned(IN_Data) <= unsigned(IN_threshold) then
            special <= "01";
          elsif IN_Data(INPUT_DATA_WIDTH-1 downto 2) = "11111111" then  --as bit 8 and 9 are '1' this can't be hadronic
            case IN_Data(1 downto 0) is
              when "00" =>
                special <= "00";                                        -- 1020 is not special
              when "11" =>
                special <= "10";                                        --saturated
              when others =>
                special <= "01";                                        -- 1021 and 1022 are to be zeroed
            end case;
          else
            special <= "00";
          end if;
        else
          special <= special;
        end if;
      end if;
    end process special_proc;
 
 
    out_proc : process (clk)
    begin
      if rising_edge(clk) then
        case special is
          when "01" =>
            OUT_Data <= "0000000000000000";
          when "10" =>
            OUT_Data <= "1111111111111111";
          when others =>
            OUT_Data <= OutData;
        end case;
      end if;
    end process out_proc;
 
  end generate;
 
end architecture str;