ipbus_outputRAM_wrapper.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library ipbus_lib;
 
use ipbus_lib.ipbus.all;
use work.DataTypes.all;
use work.AlgoDataTypes.all;
 
entity ipbus_outputRAM_wrapper is
  port(
    clk_ipb : in  std_logic;
    rst     : in  std_logic;
    ipb_in  : in  ipb_wbus;
    ipb_out : out ipb_rbus;
    AlgoIn  : in  AlgoOutput;
 
    BCNIn     : in std_logic_vector(11 downto 0);
    SpyBCNIn  : in std_logic := '0';
    
    rclk    : in  std_logic;
    Sync    : in  std_logic;
    we      : in  std_logic := '0';
    AlgoOut : out AlgoTriggerObjects(7 downto 0)
    );
 
end ipbus_outputRAM_wrapper;
 
architecture rtl of ipbus_outputRAM_wrapper is
 
  component AlgoOutputRAM
    port (
      clka  : in  std_logic;
      ena   : in  std_logic;
      wea   : in  std_logic_vector(0 downto 0);
      addra : in  std_logic_vector(9 downto 0);
      dina  : in  std_logic_vector(31 downto 0);
      douta : out std_logic_vector(31 downto 0);
      clkb  : in  std_logic;
      enb   : in  std_logic;
      web   : in  std_logic_vector(0 downto 0);
      addrb : in  std_logic_vector(6 downto 0); 
      dinb  : in  std_logic_vector(255 downto 0);
      doutb : out std_logic_vector(255 downto 0)
      );
  end component;
 
 
  -- algorithm signals
  signal din                          : std_logic_vector(255 downto 0);
  signal q                            : std_logic_vector(255 downto 0);
  signal counter                      : std_logic_vector(6 downto 0) := "0000000";  --16 BCs*5TOBs
  signal BC_counter                   : std_logic_vector(3 downto 0) := "0000";  --16 BCs*5TOBs
  signal S1                           : std_logic                    := '0';
  signal AlgoOut3, AlgoOut2, AlgoOut1 : AlgoTriggerObjects(7 downto 0);
 
 
  --ipbus signals
  signal ack          : std_logic;
  signal ack2         : std_logic;
  signal ipbus_write  : std_logic_vector(0 downto 0);
  signal write_enable : std_logic_vector(0 downto 0);
 
begin
  IPBUS_RAM : process(clk_ipb)
  begin
    if rising_edge(clk_ipb) then
      if ipb_in.ipb_strobe = '1' and ipb_in.ipb_write = '1' then
        ipbus_write(0) <= '1';
      else
        ipbus_write(0) <= '0';
      end if;
      ack2 <= ipb_in.ipb_strobe and (not ack2) and (not ack);
      ack  <= ack2;
 
    end if;
  end process;
 
  ipb_out.ipb_ack <= ack;
  ipb_out.ipb_err <= '0';
  write_enable(0) <= we;
 
  COUNTER_PROC : process(rclk)
  begin
    if rising_edge(rclk) then
      S1 <= Sync;
      if S1 = '1' then
        BC_counter <= std_logic_vector(unsigned(BC_counter) + 1);
      end if;
 
      if BC_Counter = "0000" and S1 = '1' then
        counter <= (others => '0');
      else
        counter <= std_logic_vector(unsigned(counter) + 1);
      end if;
 
      -- Output is sync'ed with next BC
      AlgoOut  <= AlgoOut1;
      AlgoOut1 <= AlgoOut2;
      AlgoOut2 <= AlgoOut3;
    end if;
  end process;
 
  ALGO_OUTPUT_RAM : AlgoOutputRAM
    port map (
      clka  => clk_ipb,
      ena   => ipb_in.ipb_strobe,
      wea   => ipbus_write,
      addra => ipb_in.ipb_addr(9 downto 0),
      dina  => ipb_in.ipb_wdata,
      douta => ipb_out.ipb_rdata,
      clkb  => rclk,
      enb   => '1',
      web   => write_enable,
      addrb => counter,
      dinb  => din,
      doutb => q
      );
 
  -- Conversion between algorithm data-types and std_logic_vectors 
  AlgoOut3 <= to_AlgoTriggerObjects(to_AlgoOutput(q));
 
  din      <= to_LogicVector(AlgoIn) when spyBCNIn = '0'  else to_LogicVector(AlgoIn)(din'high - 32 downto 0) & x"f" & x"0" & BCNIn  & x"fff";
 
end rtl;