rtl Architecture Reference

IPBus wrapper for output spy/playback RAM for Algorithm module. More...

Processes
IPBUS_RAM	( clk_ipb )
COUNTER_PROC	( rclk )
	Synchronize the counter with RAM, accounting for latency.

Components
AlgoOutputRAM
	Address space to contain 16 BCs*5TOBS.

Signals
din	std_logic_vector ( 255 downto 0 )
q	std_logic_vector ( 255 downto 0 )
counter	std_logic_vector ( 6 downto 0 ) := " 0000000 "
BC_counter	std_logic_vector ( 3 downto 0 ) := " 0000 "
S1	std_logic := ' 0 '
AlgoOut3	AlgoTriggerObjects ( 7 downto 0 )
AlgoOut2	AlgoTriggerObjects ( 7 downto 0 )
AlgoOut1	AlgoTriggerObjects ( 7 downto 0 )
ack	std_logic
ack2	std_logic
ipbus_write	std_logic_vector ( 0 downto 0 )
write_enable	std_logic_vector ( 0 downto 0 )

Instantiations
algo_output_ram	algooutputram
	Xilinx IP output RAM.

Detailed Description

IPBus wrapper for output spy/playback RAM for Algorithm module.

This RAM contains algorithm output data, i.e. the Trigger Objects or TOBs having a width of 32 bits. It can be used to spy or for playback. It can contain 16*5 TOBs, so TOBs produced during 16 BCs can be stored or played back.

The internal memory, AlgoOutputRAM is a real dual port RAM Xilinx IP. The Algorithm uses the RAM port b having a width of 256 bit, i.e. 8 * 32-bit TOBs. In fact, the Algorithm can produce a maximum of 8 TOBs per BC.

Ipbus uses AlgoOutputRAM port a having a width of 32 bits. The depth of the RAM is in this case 16*5 = 80 The ipbus RAM contains data as follows:

BC	bits 0-31
BC 1	TOB0
BC 1	TOB1
BC 1	TOB2
BC 1	TOB3
BC 1	TOB4
BC 2	TOB0
BC 2	TOB1
BC 2	TOB2
BC 2	TOB3
BC 2	TOB4
BC...	TOB0
BC...	TOB1
BC...	TOB2
BC...	TOB3
BC...	TOB4
BC 16	TOB0
BC 16	TOB1
BC 16	TOB2
BC 16	TOB3
BC 16	TOB4

Author

Francesco Gonnella

Definition at line 76 of file ipbus_outputRAM_wrapper.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/ipbus_outputRAM_wrapper.vhd