IPBusTopAlgoModule.vhd File Reference

Top feature extracting algorithm module with IPBus interface. More...

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Entities
IPBusTopAlgoModule	entity
	Top feature extracting algorithm module with IPBus interface. More...
Behavioral	architecture
	Top feature extracting algorithm module with IPBus interface. More...

Detailed Description

Top feature extracting algorithm module with IPBus interface.

The feature extracting module runs at 200 MHz, i.e. 5 times faster than the BC frequency. So data belonging to a Bunch Crossing (BC) can be handled in 5 clock cycles. An eFEX FPGA handles 60 input Trigger Towers (TT) among which 40 are core towers, i.e. a TOB must be produced for each of them and 20 are used just as environment.

In order to produce 40 TOBs per BC, 40 independent Algorithm Cores (ACs) should process data in parallel. Thanks to the higher frequency, 8 ACs are enough to process data presented to the cores in 5 clock cycles. It is possible to handle a region of 0.7 Eta * 0.8 Phi.

In case the eFEX module is handling a border region in Eta, a number of environment-only TT must be used as core. This means that real data from the column at the far left end (or right) is not provided by the calorimeter. In this case, dummy data (e.g. all zeroes) are fed to the ACs. This module uses 2 clocks: 200 MHz and 280 MHz, plus a 40 MHz 12% duty cyle Load clock. The 200MHz, the Load and the 40MHz clocks must be in phase when the Load is high, as shown in figure.

            ┌───────┐       ┌───────┐       ┌───────┐       ┌───
 CLK40:    ─┘       └───────┘       └───────┘       └───────┘
            ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
 CLK200:   ─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─
            ┌┐              ┌┐              ┌┐              ┌┐
 Load:    ──┘└──────────────┘└──────────────┘└──────────────┘└──
          ──┬───────────────┬───────────────┬───────────────┬───
 Data:      │   DATA BC1    │   DATA BC2    │   DATA BC3    │
          ──┴───────────────┴───────────────┴───────────────┴───

The output frequency of this module is 280 MHz, 7 times 40 MHz. Only 5 TOBs per BC can be produced, so no tob will be transmitted in the last 2 clock cycles The output timing is represented in figure

            ┌──────┐      ┌──────┐      ┌
 CLK40:    ─┘      └──────┘      └──────┘
            ┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌
 CLK280:   ─┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘
            ┌┐            ┌┐            ┌
 Start:   ──┘└────────────┘└────────────┘
          ──┬─┬─┬─┬─┬─┬───┬─┬─┬─┬─┬─┬───┬
 TOB out:   │1│2│3│4│5│   │1│2│3│4│5│   │
          ──┴─┴─┴─┴─┴─┴───┴─┴─┴─┴─┴─┴───┴

A multicycle constraint of 2 is used to cross the clock domains from 40 to 200MHz and from 200 to 280 MHz.

Author

Francesco Gonnella

Definition in file IPBusTopAlgoModule.vhd.