LoadGenerator Entity Reference

Load generator. More...

Inheritance diagram for LoadGenerator:

Entities
Behavioral	architecture
	Load generator. More...

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Generics
PHASE200	integer := 2
PHASE280	integer := 3

Ports
IN_Load	in	std_logic
CLK200	in	std_logic
CLK280	in	std_logic
OUT_Load200	out	std_logic
OUT_Load280	out	std_logic

Detailed Description

Load generator.

This module generates a load signal for algorithm data. It is derived from the load clock, having a 40 MHz frequency a 12% duty cycle (shorter than 200MHz and 280MHz. The OUT_Load200 and 280 signals are synchronised with the 200 and 280 MHz clock The two phases should be set according to the simulation and to the multicycle constraints: 40 to 200 and 200 to 280

Author

Francesco Gonnella

Definition at line 17 of file LoadGenerator.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/LoadGenerator.vhd