Behavioral Architecture Reference

Load generator. More...

Processes
PROCESS_5	( IN_Load )
PROCESS_6	( CLK200 )
PROCESS_7	( CLK280 )

Signals
LoadR	std_logic := ' 0 '
Load280_i	std_logic := ' 0 '
Load_delay280	std_logic_vector ( PHASE280 downto 0 ) := ( others = > ' 0 ' )
Load_delay200	std_logic_vector ( PHASE200 downto 0 ) := ( others = > ' 0 ' )

Attributes
keep	string
max_fanout	integer
keep	signal is " true "
max_fanout	signal is 40

Detailed Description

Load generator.

This module generates a load signal for algorithm data. It is derived from the load clock, having a 40 MHz frequency a 12% duty cycle (shorter than 200MHz and 280MHz. The OUT_Load200 and 280 signals are synchronised with the 200 and 280 MHz clock The two phases should be set according to the simulation and to the multicycle constraints: 40 to 200 and 200 to 280

Author

Francesco Gonnella

Definition at line 30 of file LoadGenerator.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/LoadGenerator.vhd