AlgoParameterRAM_wrapper Entity Reference

Parameter RAM wrapper. More...

Inheritance diagram for AlgoParameterRAM_wrapper:

Entities
rtl	architecture
	Parameter RAM wrapper. More...

Libraries
IEEE
ipbus_lib

Use Clauses
STD_LOGIC_1164
numeric_std
ipbus
DataTypes	Package <DataTypes>

Ports
clk_ipb	in	std_logic
rst	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
rclk	in	std_logic
we	in	std_logic := ' 0 '
q	out	std_logic_vector ( PARAMETER_RAM_DATA_WIDTH- 1 downto 0 )
addr	in	std_logic_vector ( 2 downto 0 )

Detailed Description

Parameter RAM wrapper.

This was generalised from ipbus dpram. This ram is 512 bit wide and 5 word deep. All the parameters should fit in one word, and the five words will cover the 5 eta values.

The RAM is also accessed via ipbus in chunks of 32 bits. From ipbus point of view the RAM is 32-bit wide and 64-word deep.

The RAM data format is implemented in IPBusTopAlgoModule.vhd where the signals are connected to the RAM.

The following table represent the RAM data format as seen from ipbus. Only the first 16 words are represented. The following words have the same structure for the greater eta values:

• Words 0 to 7 eta = 0
• Words 8 to 15 eta = 1
• Words 16 to 23 eta = 2
• Words 24 to 31 eta = 3
• Words 32 to 39 eta = 4

	0:7	8:15	16:23	24:31
0	Reta0	Reta1	Reta2	DMC layer0 mask
1	Ws0	Ws1	Ws2	DMC layer1 mask
2	Had0	Had1	Had2	DMC layer2 mask
3	eg E thr(15:8)	eg E thr(7:0)	eg iso thr (15:8)	eg iso thr (7:0)
4	Frac0	Frac1	Frac2	DMC layer3 mask
5	Jet0	Jet1	Jet2
6	Tau E thr(15:8)	Tau E thr(7:0)	tau iso thr(15:8)	tau iso thr (7:0)
7	Tau min E Thr(15:8)	Tau min E thr(7:0)

Author

Francesco Gonnella, David Reikher

Definition at line 45 of file AlgoParameterRAM_wrapper.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/AlgoParameterRAM_wrapper.vhd