eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

Back to eFEX documentation
Components | Instantiations | Processes | Signals
rtl Architecture Reference

Parameter RAM wrapper. More...

Processes

IPBUS_RAM  ( clk_ipb )

Components

AlgoParameterRAM 

Signals

ram_ena  std_logic
ram_wea  std_logic_vector ( 0 downto 0 )
ram_addra  std_logic_vector ( PARAMETER_RAM_ADDR_WIDTH- 1 downto 0 )
ram_dina  std_logic_vector ( 31 downto 0 )
ram_douta  std_logic_vector ( 31 downto 0 )
ram_clkb  std_logic
ram_enb  std_logic
ram_web  std_logic_vector ( 0 downto 0 )
ram_addrb  std_logic_vector ( 2 downto 0 )
ram_dinb  std_logic_vector ( PARAMETER_RAM_DATA_WIDTH- 1 downto 0 )
ram_doutb  std_logic_vector ( PARAMETER_RAM_DATA_WIDTH- 1 downto 0 )
ack  std_logic
ack2  std_logic
ipbus_write  std_logic_vector ( 0 downto 0 )
write_enable  std_logic_vector ( 0 downto 0 )

Instantiations

algo_parameter_ram  algoparameterram

Detailed Description

Parameter RAM wrapper.

This was generalised from ipbus dpram. This ram is 512 bit wide and 5 word deep. All the parameters should fit in one word, and the five words will cover the 5 eta values.

The RAM is also accessed via ipbus in chunks of 32 bits. From ipbus point of view the RAM is 32-bit wide and 64-word deep.

The RAM data format is implemented in IPBusTopAlgoModule.vhd where the signals are connected to the RAM.

The following table represent the RAM data format as seen from ipbus. Only the first 16 words are represented. The following words have the same structure for the greater eta values:

0:7 8:15 16:23 24:31
0 Reta0 Reta1 Reta2 DMC layer0 mask
1 Ws0 Ws1 Ws2 DMC layer1 mask
2 Had0 Had1 Had2 DMC layer2 mask
3 eg E thr(15:8) eg E thr(7:0) eg iso thr (15:8) eg iso thr (7:0)
4 Frac0 Frac1 Frac2 DMC layer3 mask
5 Jet0 Jet1 Jet2
6 Tau E thr(15:8) Tau E thr(7:0) tau iso thr(15:8) tau iso thr (7:0)
7 Tau min E Thr(15:8) Tau min E thr(7:0)
Author
Francesco Gonnella, David Reikher

Definition at line 59 of file AlgoParameterRAM_wrapper.vhd.


The documentation for this class was generated from the following file: