AlgoRateMonitor.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
 
library infrastructure_lib;
use infrastructure_lib.counter;
 
use work.DataTypes.all;
use work.AlgoDataTypes.all;
 
library ipbus_lib;
use ipbus_lib.ipbus_reg_types.all;
use ipbus_lib.ipbus.all;
 
entity AlgoRateMonitor is
  port (
    ipb_clk : in  std_logic;
    ipb_rst : in  std_logic;
    ipb_in  : in  ipb_wbus;
    ipb_out : out ipb_rbus;
 
    clk      : in std_logic;
    IN_BCN   : in std_logic_vector(11 downto 0);  --@suppress
    IN_synch : in std_logic;
    IN_eta   : in std_logic_vector(2 downto 0);
 
    IN_eg_energies : in array_std_logic_vector(OUTPUT_TOBS-1 downto 0)(ENERGY_WIDTH-1 downto 0);
    IN_eg_valids   : in std_logic_vector(OUTPUT_TOBS-1 downto 0);
 
    IN_tau_energies : in array_std_logic_vector(OUTPUT_TOBS-1 downto 0)(ENERGY_WIDTH-1 downto 0);
    IN_tau_valids   : in std_logic_vector(OUTPUT_TOBS-1 downto 0));
 
end AlgoRateMonitor;
 
 
architecture Behavioral of AlgoRateMonitor is
  constant N_CTRL : positive := 2;
  constant N_STAT : positive := 98;
 
  signal write_reg : ipb_reg_v(N_STAT - 1 downto 0) := (others => (others => '0'));
  signal read_reg  : ipb_reg_v(N_CTRL - 1 downto 0);
 
  signal enable, counter_reset, reset, sync        : std_logic;
  signal energy_threshold_eg, energy_threshold_tau : std_logic_vector(ENERGY_WIDTH-1 downto 0);
  signal sync_d                                    : std_logic_vector (2 downto 0);
  signal counter_start, counter_stop               : std_logic;
  signal status, control                           : std_logic_vector(31 downto 0);
 
  signal right_eta               : std_logic_vector(5 downto 0);
  signal eta_eg, eta_tau         : std_logic_vector(7 downto 0);
  signal normalisation_saturated : std_logic;
 
  type STATE_TYPE is (ready, idle, run);
  signal state : STATE_TYPE;
 
--  ####### attributes  ########
    attribute keep       : string ;
    attribute max_fanout : integer;
    attribute keep of       read_reg : signal is "true" ;
    attribute max_fanout of read_reg : signal is 1000;
    attribute keep of       reset : signal is "true" ;
    attribute max_fanout of reset : signal is 1000;
 
 
begin
  IPBUS_ALGO_REGISTERS : entity ipbus_lib.ipbus_ctrlreg_v
    generic map (               -- @suppress "Generic map uses default values. Missing optional actuals: SWAP_ORDER"
      N_CTRL => N_CTRL,         --number of control reg
      N_STAT => N_STAT)         --number of status reg
    port map (                  -- @suppress "Port map uses default values. Missing optional actuals: ctrl_default, qmask"
      clk       => ipb_clk,
      reset     => ipb_rst,
      ipbus_in  => ipb_in,
      ipbus_out => ipb_out,
      d         => write_reg,
      q         => read_reg,
--    qmask     => (others => '0'),
      stb       => open);
 
  control              <= read_reg(0);
  energy_threshold_eg  <= read_reg(1)(15 downto 0);
  energy_threshold_tau <= read_reg(1)(31 downto 16);
 
  write_reg(N_STAT-1) <= status;
 
  -- registers connections
  counter_start <= control(0);
  counter_stop  <= control(1);
  counter_reset <= control(2);
 
  synch_delay : process (clk)
  begin
    if rising_edge(clk) then
      sync_d(0)          <= IN_synch;
      sync_d(2 downto 1) <= sync_d(1 downto 0);
      sync               <= sync_d(2);
    end if;
  end process;
 
 
  enable_proc : process (clk)
  begin
    if rising_edge(clk) then
      if sync = '1' then
        if counter_reset = '1' then
          state  <= ready;
          reset  <= '1';
          enable <= '0';
        else
          case state is
            when idle =>        -- @suppress "Dead state 'idle': state does not have outgoing transitions"
              state <= idle;
              reset <= '0';
 
            when ready =>
              if counter_start = '1' then
                state  <= run;
                reset  <= '0';
                enable <= '1';
              else
                state  <= ready;
                reset  <= '1';
                enable <= '0';
              end if;
 
            when run =>
              if counter_stop = '1' then
                state  <= idle;
                reset  <= '0';
                enable <= '0';
              else
                state  <= run;
                reset  <= '0';
                enable <= '1';
              end if;
          end case;
        end if;
      else
        state  <= state;
        enable <= enable;
        reset  <= reset;
      end if;
    end if;
  end process;
 
  -- status connections
  status(1 downto 0) <= "11" when state = run else
                        "01" when state = ready else
                        "00";   --idle
  status(2) <= enable;
  status(3) <= reset;
 
 
  eg_tau_for : for phi in OUTPUT_TOBS-1 downto 0 generate
    eta_eg(phi)  <= '1' when IN_eg_valids(phi) = '1' and not (unsigned(IN_eg_energies(phi)) < unsigned(energy_threshold_eg))    else '0';
    eta_tau(phi) <= '1' when IN_tau_valids(phi) = '1' and not (unsigned(IN_tau_energies(phi)) < unsigned(energy_threshold_tau)) else '0';
  end generate;
 
  eta_for : for eta in 5 downto 0 generate
    right_eta(eta) <= '1' when unsigned(IN_eta) = eta else '0';
    phi_for : for phi in OUTPUT_TOBS-1 downto 0 generate
      CNT_EG : entity infrastructure_lib.counter
        generic map (DEPTH => 32)
        port map (
          clk     => clk,
          enable1 => enable and right_eta  (eta),
          enable2 => eta_eg(phi) and not normalisation_saturated,
          count   => write_reg(phi*6 + eta),
          reset   => reset
          );
 
      CNT_TAU : entity infrastructure_lib.counter
        generic map (DEPTH => 32)
        port map (
          clk     => clk,
          enable1 => enable and right_eta  (eta),
          enable2 => eta_tau(phi) and not normalisation_saturated,
          count   => write_reg(48 + phi*6 + eta),
          reset   => reset
          );
    end generate;
  end generate;
 
 
  NORMALISATION_CNT : entity infrastructure_lib.counter
    generic map (DEPTH => 32)
    port map (
      clk       => clk,
      enable1   => enable,
      enable2   => IN_synch,    --this shouldn't be delayed to be in time with data
      count     => write_reg(N_STAT-2),
      saturated => normalisation_saturated,
      reset     => reset
      );
 
end Behavioral;