counter Entity Reference

Counter with double enable. More...

Inheritance diagram for counter:

Entities
Behavioral	architecture
	Counter with double enable. More...

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Generics
DEPTH	integer := 16

Ports
clk	in	std_logic
		clock
enable1	in	std_logic
		enable 1
enable2	in	std_logic := ' 1 '
		enable 2
count	out	std_logic_vector ( DEPTH- 1 downto 0 )
		counter value
saturated	out	std_logic
		counter value
reset	in	std_logic
		reset

Detailed Description

Counter with double enable.

If the maximum is reache dthe counter will hold its value

Author

Francesco Gonnella

Mohammes Siyad

Saeed Taghavi

Definition at line 12 of file counter.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd