Behavioral Architecture Reference

Processes
synch_delay	( clk )
	This process delays sync by 4 so to anticipate it by 1.
enable_proc	( clk )

Constants
N_CTRL	positive := 2
	Number of control IPBus reg.
N_STAT	positive := 98
	Number of status IPBus reg.

Types
STATE_TYPE	( ready , idle , run )

Signals
write_reg	ipb_reg_v ( N_STAT - 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
read_reg	ipb_reg_v ( N_CTRL - 1 downto 0 )
enable	std_logic
counter_reset	std_logic
reset	std_logic
sync	std_logic
energy_threshold_eg	std_logic_vector ( ENERGY_WIDTH- 1 downto 0 )
energy_threshold_tau	std_logic_vector ( ENERGY_WIDTH- 1 downto 0 )
sync_d	std_logic_vector ( 2 downto 0 )
counter_start	std_logic
counter_stop	std_logic
status	std_logic_vector ( 31 downto 0 )
control	std_logic_vector ( 31 downto 0 )
right_eta	std_logic_vector ( 5 downto 0 )
eta_eg	std_logic_vector ( 7 downto 0 )
eta_tau	std_logic_vector ( 7 downto 0 )
normalisation_saturated	std_logic
state	STATE_TYPE

Attributes
keep	string
max_fanout	integer
keep	signal is " true "
max_fanout	signal is 1000

Instantiations
ipbus_algo_registers	ipbus_ctrlreg_v
	Algo Rate Monitor.
cnt_eg	counter <Entity counter>
cnt_tau	counter <Entity counter>
normalisation_cnt	counter <Entity counter>

Detailed Description

Definition at line 48 of file AlgoRateMonitor.vhd.

Member Data Documentation

ipbus_algo_registers

ipbus_algo_registers ipbus_ctrlreg_v

Instantiation

Algo Rate Monitor.

Algorithm TOB output rate monitor

Author

Francesco Gonnella

Definition at line 91 of file AlgoRateMonitor.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/AlgoRateMonitor.vhd