ctrl_playback_ram.vhd

Go to the documentation of this file.

 
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY ctrl_playback_ram IS
   PORT( 
      clk   : IN     std_logic;
      rdy   : IN     std_logic;
      reset : IN     std_logic;
      bcr   : IN     std_logic;
      addr  : OUT    std_logic_vector (3 DOWNTO 0);
      en    : OUT    std_logic     
      
   );
 
 
 
END ENTITY ctrl_playback_ram ;
 
ARCHITECTURE Behavioral OF ctrl_playback_ram IS
signal addr_ram:unsigned (3 downto 0):= "0000";
 
   TYPE STATE_TYPE IS (
      idle,
      rd_en,
      bcr_done
   );
 
 SIGNAL current_state : STATE_TYPE;
 
BEGIN
 
   clocked_proc : PROCESS ( clk,reset)
   
   BEGIN
      IF (reset = '1') THEN
         current_state <= idle;
         addr <= (others => '0');
         en <= '0';
      ELSIF (clk'EVENT AND clk = '1') THEN
 
          CASE current_state IS
            WHEN idle => 
               addr <= (others=> '0');
               addr_ram <= (others=> '0');
               en <= '0';
               IF (rdy ='1') THEN 
                  current_state <= rd_en;
               ELSE
                  current_state <= idle;
               END IF;
            WHEN rd_en => 
               addr_ram <= addr_ram +1 ;
               addr <= std_logic_vector(addr_ram);
               en <= '1';
               IF (rdy = '0') THEN 
                  current_state <= idle;
               ELSIF (bcr ='1') THEN 
                  current_state <= bcr_done;
               ELSE
                  current_state <= rd_en;
               END IF;
            WHEN bcr_done => 
               addr <= (others => '0');
               addr_ram <= "0001";
               en <= '1';
               current_state <= rd_en;
            WHEN OTHERS =>
               current_state <= idle;
         END CASE;
      END IF;
   END PROCESS clocked_proc;
 
END ARCHITECTURE Behavioral;