ctrl_playback_ram Entity Reference

control State machine of playback ram More...

Inheritance diagram for ctrl_playback_ram:

Entities
Behavioral	architecture
	control State machine of playback ram More...

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith

Ports
clk	in	std_logic
		rx clock of 40 Mhz
rdy	in	std_logic
		ready
reset	in	std_logic
		reset
bcr	in	std_logic
		bcr in
addr	out	std_logic_vector ( 3 DOWNTO 0 )
		ram address for read side
en	out	std_logic
		ram enable

Detailed Description

control State machine of playback ram

This state machine controls the read side of the input spy/playback RAM. When the ram is writen and rdy signal is set the state machine will start to enable and address the read side of the dual port ram. It will generate kchar of the data for the frame.

Author

Mohammed Siyad

Francesco Gonnella

Definition at line 16 of file ctrl_playback_ram.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/ctrl_playback_ram.vhd