latch_enable.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
LIBRARY xil_defaultlib;
 
 
entity latch_enable is
  Port ( 
     clk_280m    : IN     std_logic;
     MGT_COMMADET : IN     std_logic;
     latch_enable  : OUT    std_logic
     
     );
end latch_enable;
architecture Behavioral of latch_enable is
 
signal cntr     : unsigned(3 downto 0):= "0000";
 
 
begin
 
 
 process (clk_280m)
 
      begin
          if clk_280m'  event and clk_280m  ='1'  then
          latch_enable  <='0';
          cntr <= cntr +1;
            if  (MGT_COMMADET ='1' )then
                cntr <="0010";
            end if;  
         
            if (cntr = 6  and  MGT_COMMADET ='0'  ) then
                latch_enable  <='1';
                cntr <="0000";
            end if;
       end if;
   end process;    
         
         
end Behavioral;