synch_stg_1.vhd File Reference

First Stage Synchronisation of process FPGA. More...

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Entities
synch_stage_1	entity
	First Stage Synchronisation of process FPGA. More...
Behavioral	architecture
	First Stage Synchronisation of process FPGA. More...

Detailed Description

First Stage Synchronisation of process FPGA.

In the first stage of the synchronisation performs following tasks:

• It measures the time between the arrival of MGT_commadet and the rising edge of ttc_clk and save the value to register.
• Synchronises SIPO in first stage to form a parallel data of the incoming rx data of 280MHz data
• Sets length of pipeline in the first stage, under control of state_machine
• latch when data ready of 226 bits.

First Stage Synchronisattion

Author

Mohammed Siyad

Definition in file synch_stg_1.vhd.