RTL Architecture Reference

Top of Sorting XTOBs module for process FPGA. More...

Processes
U6_XTOB_clk280_proc	( clk_280M_in )

Constants
DLY	time := 0 ns

Signals
TOB_valid_out_i	array_8_of_5b
SIPO_TOB_out_i	array_8_of_240b
XTOB_sync_out_i	STD_LOGIC_VECTOR ( 7 downto 0 )
DPR_XTOBs_in_i	array_8_of_252b
DPR_XTOBs_out_i	array_8_of_252b
FIFO_XTOB_data_out_i	array_8_of_252b
XTOB_FIFO_wr_data_count_i	array_8_of_9b
XTOB_FIFO_rd_data_count_i	array_8_of_9b
DPR_XTOB_rd_addr_i	STD_LOGIC_VECTOR ( 8 downto 0 )
DPR_XTOB_wr_addr_i	STD_LOGIC_VECTOR ( 8 downto 0 )
DRP_XTOB_rd_en_i	STD_LOGIC
FIFO_XTOB_wr_en_i	STD_LOGIC
FIFO_XTOB_rd_en_i	STD_LOGIC
XTOB_FIFO_valid_i	STD_LOGIC_VECTOR ( 7 downto 0 )
XTOB_FIFO_valid_tmp	STD_LOGIC
XTOB_FIFO_full_i	STD_LOGIC_VECTOR ( 7 downto 0 )
XTOB_FIFO_full_tmp	STD_LOGIC
XTOB_FIFO_empty_i	STD_LOGIC_VECTOR ( 7 downto 0 )
XTOB_FIFO_empty_tmp	STD_LOGIC
XTOB_FIFO_prog_full_i	STD_LOGIC_VECTOR ( 7 downto 0 )
XTOB_FIFO_prog_full_tmp	STD_LOGIC
ALGO_XTOB_BCN_out_i	std_logic_vector ( 6 downto 0 )

Attributes
TIG	string
TIG	signal is " true "
keep	string
max_fanout	integer
keep	signal is " true "
max_fanout	signal is 30

Instantiations
u1_tobs_wr_fsm	fsm_TOB_wr_to_FIFO <Entity fsm_TOB_wr_to_FIFO>
u2_xtob_bcn_delay	GeneralDelay <Entity GeneralDelay>
u2_xtobs_eg	SIPO_unit <Entity SIPO_unit>
u3_xtob_drp	dpr_252b_512
u5_xtobs_fifo	fifo_252b_512

Detailed Description

Top of Sorting XTOBs module for process FPGA.

This module interfaces with 8 ALGO Blocks, receives 8 x (5 x 48-bit XTOBs + 5-b valid) signals in series, The module consists of an SIPO unit, together with an FSM for handling input data, Circular DPRAM and de-randomisation FIFO.

The SIPO unit sorts input XTOB data into 8 streams of 252b = (5 x 48-bit word) + 5-bit valid + 7-bit XTOB_BCN word to store in Circular DPRAM. The SIPO data of 252b is saved every Bunch Crossing tick to enable multi-slice readout.

The 252-b XTOB data is transferred from Circular DPRAM into derandomisation FIFO upon arraival of L1A.

Only Process FPGA 1 and 2 transmit e/g and tau events to TOPO, and the off-line Readout. Process FPGA 3 and 4 do not transmit to TOPO instead they send their TOBs to Process FPGA 1 and 2, and transmit XTOB only events to the Control FPGA.

Author

Saeed Taghavi

Definition at line 92 of file XTOBs_sorting.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/XTOBs_sorting.vhd