XTOBs_sorting Entity Reference

Top of Sorting XTOBs module for process FPGA. More...

Inheritance diagram for XTOBs_sorting:

Entities
RTL	architecture
	Top of Sorting XTOBs module for process FPGA. More...

Libraries
ieee
UNISIM
TOB_rdout_lib
algolib
Infrastructure_lib

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS
data_type_pkg	Package <data_type_pkg>
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
AlgoDataTypes	Package <AlgoDataTypes>

Generics
FPGA_NUMBER	integer := 1
	Integer used to distinguish different FPGAs having a slightly different firmware.

Ports
L1A_in	in	STD_LOGIC
		L1A signal input.
XTOB_FIFO_sw_rst	in	std_logic
		TOB Readout FIFO reset Pulse by software command OR SYS_RST.
XTOB_512b_in	in	AlgoXOutput
		array 8 x 64b words XTOBs
XTOB_Valid_flg_in	in	STD_LOGIC_VECTOR ( 7 downto 0 )
		8b XTOB has valid data
XTOB_sync_in	in	STD_LOGIC
		XTOB sync signal.
ALGO_XTOB_BCN_in	in	std_logic_vector ( 6 downto 0 )
		sorted XTOB BCN with delay through ALGO/sorting block
pre_ld_wr_addr_XTOB	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		latency pre-load for XTOB DRPAM write address
DPR_locations_to_rd	in	STD_LOGIC_VECTOR ( 2 downto 0 )
		number of multi-slice locations to read from DPRAM
trigger_slice_in	in	STD_LOGIC_VECTOR ( 3 downto 0 )
		Trigger slice number - on L1A.
FIFO_rd_en	in	STD_LOGIC
		read XTOB data into Shift Registers
clk_200M_in	in	STD_LOGIC
		200Mhz input signal
clk_280M_in	in	STD_LOGIC
		280Mhz input signal
XTOB_FIFO_pFULL_THRESH_assert	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		Threshold to assert XTOB FIFO prog full flag.
XTOB_FIFO_pFULL_THRESH_negate	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		Threshold to negate XTOB FIFO prog full flag.
FIFO_XTOB_data_out	out	array_8_of_252b
		XTOBs output of fifo {array 8 of [(5*48b) + 5b valid] + 7b BCN}.
XTOB_FIFO_rd_data_count	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		occupancy of XTOB derandomisation FIFO - read count
XTOB_FIFO_valid	out	STD_LOGIC
		XTOBs FIFO data valid signal.
XTOB_FIFO_full	out	STD_LOGIC
		XTOBs FIFO full flag.
XTOB_FIFO_empty	out	STD_LOGIC
		XTOBs FIFO empty flag.
XTOB_FIFO_prog_full	out	STD_LOGIC
		XTOBs FIFO prog full flag.
xtob_data_dpram_fsm	out	STD_LOGIC_VECTOR ( 7 downto 0 )
		Monitor state machine status register.

Detailed Description

Top of Sorting XTOBs module for process FPGA.

This module interfaces with 8 ALGO Blocks, receives 8 x (5 x 48-bit XTOBs + 5-b valid) signals in series, The module consists of an SIPO unit, together with an FSM for handling input data, Circular DPRAM and de-randomisation FIFO.

The SIPO unit sorts input XTOB data into 8 streams of 252b = (5 x 48-bit word) + 5-bit valid + 7-bit XTOB_BCN word to store in Circular DPRAM. The SIPO data of 252b is saved every Bunch Crossing tick to enable multi-slice readout.

The 252-b XTOB data is transferred from Circular DPRAM into derandomisation FIFO upon arraival of L1A.

Only Process FPGA 1 and 2 transmit e/g and tau events to TOPO, and the off-line Readout. Process FPGA 3 and 4 do not transmit to TOPO instead they send their TOBs to Process FPGA 1 and 2, and transmit XTOB only events to the Control FPGA.

Author

Saeed Taghavi

Definition at line 39 of file XTOBs_sorting.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/XTOBs_sorting.vhd