SIPO_unit Entity Reference

XTOB SIPO for process FPGA. More...

Inheritance diagram for SIPO_unit:

Entities
Behavioral	architecture
	XTOB SIPO for process FPGA. More...

Libraries
IEEE
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>

Ports
XTOB_in	in	STD_LOGIC_VECTOR ( 47 downto 0 )
		33b XTOBs from 1 algo block
XTOB_valid_in	in	STD_LOGIC
		1b XTOB valid signal
XTOB_sync_in	in	STD_LOGIC
		1b synch signal input
clk_in	in	STD_LOGIC
XTOB_sync_out	out	STD_LOGIC
		1b synch signal output
XTOB_valid_out	out	STD_LOGIC_VECTOR ( 4 downto 0 )
		XTOBs valid signals 5b.
XTOB_out	out	STD_LOGIC_VECTOR ( 239 downto 0 )
		5 XTOBs (34b) * 5 = 170b

Detailed Description

XTOB SIPO for process FPGA.

This module convert 5x48b e/g or tau XTOBs into one 240b XTObs and 5b Valid signals for Circular DPRAM

Author

Saeed Taghavi

Definition at line 16 of file SIPO_unit.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/SIPO_unit.vhd