Behavioral Architecture Reference

XTOB SIPO for process FPGA. More...

Processes
U1_proc	( clk_in )

Signals
reg_1_tmp	std_logic_vector ( 47 downto 0 )
reg_2_tmp	std_logic_vector ( 47 downto 0 )
reg_3_tmp	std_logic_vector ( 47 downto 0 )
reg_4_tmp	std_logic_vector ( 47 downto 0 )
reg_5_tmp	std_logic_vector ( 47 downto 0 )
valid_1_tmp	std_logic
valid_2_tmp	std_logic
valid_3_tmp	std_logic
valid_4_tmp	std_logic
valid_5_tmp	std_logic
sync_1_tmp	std_logic
sync_2_tmp	std_logic
sync_3_tmp	std_logic
sync_4_tmp	std_logic
sync_5_tmp	std_logic

Attributes
max_fanout	integer
keep	string
keep	signal is " true "
max_fanout	signal is 60

Detailed Description

XTOB SIPO for process FPGA.

This module convert 5x48b e/g or tau XTOBs into one 240b XTObs and 5b Valid signals for Circular DPRAM

Author

Saeed Taghavi

Definition at line 36 of file SIPO_unit.vhd.

---

The documentation for this class was generated from the following file:

• Readout/src/SIPO_unit.vhd