SIPO_unit.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
library TOB_rdout_lib;
use TOB_rdout_lib.TOB_rdout_ip_pkg.ALL;
use TOB_rdout_lib.data_type_pkg.all;
 
entity SIPO_unit is
    Port (
        XTOB_in          : in STD_LOGIC_VECTOR (47 downto 0);
        XTOB_valid_in    : in STD_LOGIC ;
        XTOB_sync_in     : in STD_LOGIC;
        clk_in           : in STD_LOGIC;
        XTOB_sync_out    : out STD_LOGIC;
        XTOB_valid_out   : out STD_LOGIC_VECTOR (4 downto 0);
        XTOB_out         : out STD_LOGIC_VECTOR (239 downto 0)
 
    );
end SIPO_unit;
 
architecture Behavioral of SIPO_unit is
    signal  reg_1_tmp        : std_logic_vector(47 downto 0);  -- 34b XTOB
    signal  reg_2_tmp        : std_logic_vector(47 downto 0);
    signal  reg_3_tmp        : std_logic_vector(47 downto 0);
    signal  reg_4_tmp        : std_logic_vector(47 downto 0);
    signal  reg_5_tmp        : std_logic_vector(47 downto 0);
 
    signal  valid_1_tmp      : std_logic;    -- 1b valid XTOB
    signal  valid_2_tmp      : std_logic;
    signal  valid_3_tmp      : std_logic;
    signal  valid_4_tmp      : std_logic;
    signal  valid_5_tmp      : std_logic;
 
    signal  sync_1_tmp       : std_logic;
    signal  sync_2_tmp       : std_logic;
    signal  sync_3_tmp       : std_logic;
    signal  sync_4_tmp       : std_logic;
    signal  sync_5_tmp       : std_logic;
 
--  ####### attribute for signals  ########
    attribute max_fanout : integer;
    attribute keep       : string ;
    attribute keep of       sync_1_tmp    : signal is "true" ;
    attribute max_fanout of sync_1_tmp    : signal is 60;
    attribute keep of       XTOB_sync_out : signal is "true" ;
    attribute max_fanout of XTOB_sync_out : signal is 60;
 
BEGIN
 
U1_proc : process (clk_in)
    begin
        if(clk_in'event and clk_in = '1') then
           sync_5_tmp <= XTOB_sync_in;       -- register input sync data
           sync_4_tmp <= sync_5_tmp;
           sync_3_tmp <= sync_4_tmp;
           sync_2_tmp <= sync_3_tmp;
           sync_1_tmp <= sync_2_tmp;
 
           reg_5_tmp  <= XTOB_in ;         -- register input data
           reg_4_tmp <= reg_5_tmp;
           reg_3_tmp <= reg_4_tmp;
           reg_2_tmp <= reg_3_tmp;
           reg_1_tmp <= reg_2_tmp;
 
           valid_5_tmp  <= XTOB_valid_in ;  -- register TOB valid data
           valid_4_tmp  <= valid_5_tmp;
           valid_3_tmp  <= valid_4_tmp;
           valid_2_tmp  <= valid_3_tmp;
           valid_1_tmp  <= valid_2_tmp;
 
-- moved following statements into the process so ad 1 clk cycle pipeline
           XTOB_out        <= reg_5_tmp & reg_4_tmp & reg_3_tmp & reg_2_tmp & reg_1_tmp;
           XTOB_valid_out  <= valid_5_tmp & valid_4_tmp & valid_3_tmp & valid_2_tmp & valid_1_tmp;
           XTOB_sync_out   <= sync_1_tmp;
 
        end if;
    end process;
 
--U2_ila_XTOB_sorting : ila_ipbus_fabric_rd_wr
--PORT MAP (
--  clk    => clk_in ,
--  probe0(31 downto 0) => XTOB_in ,     -- 36b
--  probe0(35 downto 32) => (others => '0' ) ,     -- 36b
--  probe1 => (others => '0' ) ,         -- 36b
--  probe2(0) => XTOB_sync_in ,  -- 1b
--  probe3(0) => XTOB_valid_in,     -- 1b
--  probe4 => (others => '0' ),    -- 1b
--  probe5(31 downto 0)  => reg_5_tmp,    --36b
--  probe5(35 downto 32) => (others => '0' ),    --36b
--    probe6(4 downto 0)   => XTOB_valid_out,    -- 36b
--    probe6(35 downto 5)  => (others => '0' ),    -- 36b
--    probe7 => (others => '0' ),   -- 1b
--  probe8 => (others => '0' )  ,   -- 1b
--    probe9(0) => XTOB_sync_out    -- 1b
--);
 
end Behavioral;