fsm_TOB_wr_to_FIFO Entity Reference

Top of fsm_TOB_wr_to_FIFO for process FPGA. More...

Inheritance diagram for fsm_TOB_wr_to_FIFO:

Entities
Behavioral	architecture
	Top of fsm_TOB_wr_to_FIFO for process FPGA. More...

Libraries
IEEE
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>

Ports
CLK_IN	in	STD_LOGIC
		Clock input signal.
TOB_FIFO_sw_rst	in	std_logic
		TOB Readout FIFO reset Pulse by software command.
L1A_in	in	STD_LOGIC
		L1A signal input.
SIPO_sync_in	in	STD_LOGIC
		SIPO TOBs synch signal input.
pre_ld_wr_addr	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		latency pre-load for DRPAM write address
DPR_locations_to_rd	in	STD_LOGIC_VECTOR ( 2 downto 0 )
		number of multi-slice locations to read from DPRAM
trigger_slice_in	in	STD_LOGIC_VECTOR ( 3 downto 0 )
		Trigger slice number - on L1A.
DPR_rd_addr	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		DPRAM read address.
DPR_wr_addr	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		DPRAM write address.
DRP_rd_en	out	STD_LOGIC
		DPRAM read enable.
FIFO_wr_en	out	STD_LOGIC
		enable sorted TOBs write into derandomisatiion FIFO
tob_data_dpram_fsm	out	STD_LOGIC_VECTOR ( 7 downto 0 )
		Monitor state machine status register.

Detailed Description

Top of fsm_TOB_wr_to_FIFO for process FPGA.

This state machine is responsible for reading TOBs/XTObs and valid flags from Circular DPRAM and storing them into de-randomisation FIFO when the L1A signal is received.

It also controls multi-slice readout between 1 to 5 slices in sequence.

Author

Saeed Taghavi

Definition at line 22 of file fsm_TOB_wr_to_FIFO.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/fsm_TOB_wr_to_FIFO.vhd