Behavioral Architecture Reference

Top of fsm_TOB_wr_to_FIFO for process FPGA. More...

Processes
U0_clk_proc	( CLK_IN )
U3_rd_XTOB_fsm	( CLK_IN )

Types
STATE_TYPE	( idle , ser_1 , ser_2 , ser_3 , ser_4 )

Signals
SIPO_sync_in_i	std_logic
FIFO_wr_en_i	std_logic := ' 0 '
DRP_rd_en_i	std_logic
DPR_rd_addr_i	STD_LOGIC_VECTOR ( 8 downto 0 )
DPR_rd_addr_tmp	unsigned ( 8 downto 0 )
DPR_wr_addr_i	STD_LOGIC_VECTOR ( 8 downto 0 )
slice_count_i	unsigned ( 2 downto 0 )
current_state	STATE_TYPE
count	integer range 0 to 7
tmp	std_logic_vector ( 7 downto 0 )

Attributes
keep	string
max_fanout	integer
keep	signal is " true "
max_fanout	signal is 40

Instantiations
u2_rd_addr	cntr_ram_addr_9b <Entity cntr_ram_addr_9b>

Detailed Description

Top of fsm_TOB_wr_to_FIFO for process FPGA.

This state machine is responsible for reading TOBs/XTObs and valid flags from Circular DPRAM and storing them into de-randomisation FIFO when the L1A signal is received.

It also controls multi-slice readout between 1 to 5 slices in sequence.

Author

Saeed Taghavi

Definition at line 52 of file fsm_TOB_wr_to_FIFO.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/fsm_TOB_wr_to_FIFO.vhd