XTOBs_sorting.vhd File Reference

Top of Sorting XTOBs module for process FPGA. More...

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Entities
XTOBs_sorting	entity
	Top of Sorting XTOBs module for process FPGA. More...
RTL	architecture
	Top of Sorting XTOBs module for process FPGA. More...

Detailed Description

Top of Sorting XTOBs module for process FPGA.

This module interfaces with 8 ALGO Blocks, receives 8 x (5 x 48-bit XTOBs + 5-b valid) signals in series, The module consists of an SIPO unit, together with an FSM for handling input data, Circular DPRAM and de-randomisation FIFO.

The SIPO unit sorts input XTOB data into 8 streams of 252b = (5 x 48-bit word) + 5-bit valid + 7-bit XTOB_BCN word to store in Circular DPRAM. The SIPO data of 252b is saved every Bunch Crossing tick to enable multi-slice readout.

The 252-b XTOB data is transferred from Circular DPRAM into derandomisation FIFO upon arraival of L1A.

Only Process FPGA 1 and 2 transmit e/g and tau events to TOPO, and the off-line Readout. Process FPGA 3 and 4 do not transmit to TOPO instead they send their TOBs to Process FPGA 1 and 2, and transmit XTOB only events to the Control FPGA.

Author

Saeed Taghavi

Definition in file XTOBs_sorting.vhd.