busy_flag_fsm.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity busy_flag_fsm is
    generic (
        width  : integer := 32
        ); 
    Port ( 
        clk : in STD_LOGIC;
        rst : in STD_LOGIC;
        busy_flag_assert : in STD_LOGIC_VECTOR(width-1 downto 0);
        busy_flag_negate : in STD_LOGIC_VECTOR(width-1 downto 0);
        fifo_data_count  : in STD_LOGIC_VECTOR(width-1 downto 0);
        busy_flag : out STD_LOGIC := '0'
           );
end busy_flag_fsm;
 
architecture Behavioral of busy_flag_fsm is
    signal busy_flag_i : STD_LOGIC := '0';
begin
 
    busy_flag <= busy_flag_i ;  -- output to cFPGA
 
U1_proc : process (clk)
    begin
    if(clk'event and clk = '1') then
        if (rst = '1') then
            busy_flag_i <= '0' ;      -- set flag ZERO
        else
            if ( unsigned(fifo_data_count) > unsigned(busy_flag_assert) ) then 
                busy_flag_i <= '1';
            else
                if ( unsigned(fifo_data_count) < unsigned(busy_flag_negate) ) then 
                    busy_flag_i <= '0';
                end if;
            end if;
        end if;
       end if;
    end process U1_proc;
 
end Behavioral;