slave_TOB_readout.vhd File Reference

TOB/XTOB data readout slave registers. More...

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Entities
slave_TOB_readout	entity
	TOB/XTOB data readout slave registers. More...
Behavioral	architecture
	TOB/XTOB data readout slave registers. More...

Detailed Description

TOB/XTOB data readout slave registers.

This module provides IPBus access for all Read Only and Read/Write reigster withing the TOB/XTOB data readout block. Function of modules/registers are listed in the same order as VHDL code.

The IPBus bus fabric, which also has address select logic and data multiplexers. This version selects the addressed slave depending on the state of incoming control lines.

• The L1A_ID counter after receiving an L1A signal.
• The L1A_ID inserted in event header after receiving an L1A signal.
• The Bunch Crossing Number, changes every clock, reset every orbit with BCR signal.
• TOB_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing TOBs
• XTOB_EG_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing e/g XTOBs
• XTOB_TAU_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing tau XTOBs
• TOB_SLICES_TO_RD holds the value for the number of slices to read for every L1A signal.
• TRIGGER_SLICE holds the value of the Trigger slice number - on L1A.
• TOB_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert.
• TOB_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert.
• TOB_FIFO_DATA_COUNT holds the number of data words stored in the TOB FIFO.
• XTOB_EG_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert.
• XTOB_EG_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert.
• XTOB_EG_FIFO_DATA_COUNT holds the number of data words stored in the e/g XTOB FIFO.
• XTOB_TAU_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert.
• XTOB_TAU_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert.
• XTOB_TAU_FIFO_DATA_COUNT holds the number of data words stored in the tau XTOB FIFO.
• LINK_OUTPUT_FIFO_pFULL_THRESH_ASSERT holds the value for partial full threshold assert of Link Output FIFO.
• LINK_OUTPUT_FIFO_pFULL_THRESH_NEGATE holds the value for partial full threshold de-assert of Link Output FIFO.
• LINK_OUTPUT_FIFO_RD_DATA_COUNT holds the number of data words stored in the Link Output FIFO.
• TOB_data_FIFO_flags holds the status flags for BCN, TOB and XTOB FIFOs as well as Safe Mode Operation.
• SPY_TOB_MEM_WR_ADDR holds the current write address for TOB SPY Memory.
• tob_data_spy_mem: spy RAM (2K) for TOB/XTOB data to cFPGA

The TRIGGER_SLICE register is used to correctly address the DPRAM scrolling memory. In a multi-slice readout, the Read Address of DPRAM, is generated from the Write Address minus the TRIGGER_SLICE so if the TRIGGER_SLICE is the middle slice of a 3 slices readout, the first slice to be read, is the slice before the L1A, then the slice at L1A, and last slice is the slice after L1A.

Author

Saeed Taghavi

Definition in file slave_TOB_readout.vhd.