Behavioral Architecture Reference

TOB/XTOB data readout slave registers. More...

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
ipbr_d	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
BCN_in_i	std_logic_vector ( 31 downto 0 )
TOB_WR_ADDR_OFFSET_REG_i	std_logic_vector ( 31 downto 0 )
XTOB_EG_WR_ADDR_OFFSET_REG_i	std_logic_vector ( 31 downto 0 )
XTOB_TAU_WR_ADDR_OFFSET_REG_i	std_logic_vector ( 31 downto 0 )
TOB_SLICES_TO_RD_i	std_logic_vector ( 31 downto 0 ) := X " 00000001 "
TOB_FIFO_pFULL_THRESH_ASSERT_i	std_logic_vector ( 31 downto 0 )
TOB_FIFO_pFULL_THRESH_NEGATE_i	std_logic_vector ( 31 downto 0 )
TOB_FIFO_DATA_COUNT_i	std_logic_vector ( 31 downto 0 )
BCN_FIFO_pFULL_THRESH_assert_i	std_logic_vector ( 31 downto 0 )
BCN_FIFO_pFULL_THRESH_negate_i	std_logic_vector ( 31 downto 0 )
BCN_FIFO_TOB_rd_data_count_i	std_logic_vector ( 31 downto 0 )
XTOB_EG_FIFO_pFULL_THRESH_ASSERT_i	std_logic_vector ( 31 downto 0 )
XTOB_EG_FIFO_pFULL_THRESH_NEGATE_i	std_logic_vector ( 31 downto 0 )
XTOB_EG_FIFO_DATA_COUNT_i	std_logic_vector ( 31 downto 0 )
XTOB_TAU_FIFO_pFULL_THRESH_ASSERT_i	std_logic_vector ( 31 downto 0 )
XTOB_TAU_FIFO_pFULL_THRESH_NEGATE_i	std_logic_vector ( 31 downto 0 )
XTOB_TAU_FIFO_DATA_COUNT_i	std_logic_vector ( 31 downto 0 )
TOB_Link_output_FIFO_pFULL_THRESH_ASSERT_i	std_logic_vector ( 31 downto 0 )
TOB_Link_output_FIFO_pFULL_THRESH_NEGATE_i	std_logic_vector ( 31 downto 0 )
TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT_i	std_logic_vector ( 31 downto 0 )
TOB_data_FIFO_flags_i	std_logic_vector ( 31 downto 0 )
trigger_slice_i	std_logic_vector ( 31 downto 0 )
tob_busy_thresh_assert_i	STD_LOGIC_VECTOR ( 31 downto 0 )
tob_busy_thresh_negate_i	STD_LOGIC_VECTOR ( 31 downto 0 )
SPY_TOB_mem_wr_addr_i	std_logic_vector ( 31 downto 0 )
ipb_strobe_i	std_logic
ipb_write_i	std_logic

Instantiations
tob_rdout_fabric	ipbus_fabric_sel
u1_l1a_id_counter	ipbus_ctrlreg_v
u1_l1a_id_event	ipbus_ctrlreg_v
u2_bcn_in	ipbus_ctrlreg_v
u3_tob_wr_addr_offset_reg	ipbus_ctrlreg_v
u3_xtob_eg_wr_addr_offset_reg	ipbus_ctrlreg_v
u3_xtob_tau_wr_addr_offset_reg	ipbus_ctrlreg_v
u4_tob_slices_to_rd	ipbus_ctrlreg_v
u4_trigger_slice	ipbus_ctrlreg_v
u5_tob_fifo_pfull_thresh_assert	ipbus_ctrlreg_v
u6_tob_fifo_pfull_thresh_negate	ipbus_ctrlreg_v
u7_tob_fifo_data_count	ipbus_ctrlreg_v
u7_tob_busy_thresh_assert	ipbus_ctrlreg_v
u7_tob_busy_thresh_negate	ipbus_ctrlreg_v
u7_bcn_fifo_tob_rd_data_count	ipbus_ctrlreg_v
u8_xtob_eg_fifo_pfull_thresh_assert	ipbus_ctrlreg_v
u9_xtob_eg_fifo_pfull_thresh_negate	ipbus_ctrlreg_v
u10_xtob_eg_fifo_data_count	ipbus_ctrlreg_v
u8_xtob_tau_fifo_pfull_thresh_assert	ipbus_ctrlreg_v
u9_xtob_tau_fifo_pfull_thresh_negate	ipbus_ctrlreg_v
u10_xtob_tau_fifo_data_count	ipbus_ctrlreg_v
u11_link_output_fifo_pfull_thresh_assert	ipbus_ctrlreg_v
u12_link_output_fifo_pfull_thresh_negate	ipbus_ctrlreg_v
u13_link_output_fifo_rd_data_count	ipbus_ctrlreg_v
u12_tob_data_fifo_flags	ipbus_ctrlreg_v
u16_tob_mem_wr_addr	ipbus_ctrlreg_v
u17_bcn_fifo_pfull_thresh_assert	ipbus_ctrlreg_v
u18_bcn_fifo_pfull_thresh_negate	ipbus_ctrlreg_v
u19_tob_fsm_monitor	ipbus_ctrlreg_v

Detailed Description

TOB/XTOB data readout slave registers.

This module provides IPBus access for all Read Only and Read/Write reigster withing the TOB/XTOB data readout block. Function of modules/registers are listed in the same order as VHDL code.

The IPBus bus fabric, which also has address select logic and data multiplexers. This version selects the addressed slave depending on the state of incoming control lines.

• The L1A_ID counter after receiving an L1A signal.
• The L1A_ID inserted in event header after receiving an L1A signal.
• The Bunch Crossing Number, changes every clock, reset every orbit with BCR signal.
• TOB_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing TOBs
• XTOB_EG_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing e/g XTOBs
• XTOB_TAU_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing tau XTOBs
• TOB_SLICES_TO_RD holds the value for the number of slices to read for every L1A signal.
• TRIGGER_SLICE holds the value of the Trigger slice number - on L1A.
• TOB_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert.
• TOB_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert.
• TOB_FIFO_DATA_COUNT holds the number of data words stored in the TOB FIFO.
• XTOB_EG_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert.
• XTOB_EG_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert.
• XTOB_EG_FIFO_DATA_COUNT holds the number of data words stored in the e/g XTOB FIFO.
• XTOB_TAU_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert.
• XTOB_TAU_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert.
• XTOB_TAU_FIFO_DATA_COUNT holds the number of data words stored in the tau XTOB FIFO.
• LINK_OUTPUT_FIFO_pFULL_THRESH_ASSERT holds the value for partial full threshold assert of Link Output FIFO.
• LINK_OUTPUT_FIFO_pFULL_THRESH_NEGATE holds the value for partial full threshold de-assert of Link Output FIFO.
• LINK_OUTPUT_FIFO_RD_DATA_COUNT holds the number of data words stored in the Link Output FIFO.
• TOB_data_FIFO_flags holds the status flags for BCN, TOB and XTOB FIFOs as well as Safe Mode Operation.
• SPY_TOB_MEM_WR_ADDR holds the current write address for TOB SPY Memory.
• tob_data_spy_mem: spy RAM (2K) for TOB/XTOB data to cFPGA

The TRIGGER_SLICE register is used to correctly address the DPRAM scrolling memory. In a multi-slice readout, the Read Address of DPRAM, is generated from the Write Address minus the TRIGGER_SLICE so if the TRIGGER_SLICE is the middle slice of a 3 slices readout, the first slice to be read, is the slice before the L1A, then the slice at L1A, and last slice is the slice after L1A.

Author

Saeed Taghavi

Definition at line 128 of file slave_TOB_readout.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/slave_TOB_readout.vhd