eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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slave_TOB_readout.vhd
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1 
41 
42 library IEEE;
43 use IEEE.STD_LOGIC_1164.all;
44 
45 library ipbus_lib;
46 use ipbus_lib.ipbus.all;
47 
48 library TOB_rdout_lib;
49 use TOB_rdout_lib.data_type_pkg.all;
50 use TOB_rdout_lib.TOB_rdout_ip_pkg.all;
51 use TOB_rdout_lib.ipbus_decode_efex_tob_readout.all; -- TOB/XTOB readout package
52 
54 entity slave_TOB_readout is
55  port (
57  ipb_rst : in std_logic;
59  ipb_clk : in std_logic;
61  IPb_in : in ipb_wbus; -- The signals going from master to slaves
63  IPb_out : out ipb_rbus; -- The signals going from slaves to master
65  L1A_ID_Event : in std_logic_vector (31 downto 0);
67  L1A_ID : in std_logic_vector (31 downto 0);
69  BCN_in : in std_logic_vector (11 downto 0);
71  TOB_WR_ADDR_OFFSET : out std_logic_vector (8 downto 0);
73  XTOB_EG_WR_ADDR_OFFSET : out std_logic_vector (8 downto 0);
75  XTOB_TAU_WR_ADDR_OFFSET : out std_logic_vector (8 downto 0);
77  TOB_SLICES_TO_RD : out std_logic_vector (2 downto 0);
79  trigger_slice : out STD_LOGIC_VECTOR(3 downto 0) ;
81  BCN_FIFO_pFULL_THRESH_assert : out std_logic_vector(8 downto 0);
83  BCN_FIFO_pFULL_THRESH_negate : out std_logic_vector(8 downto 0);
85  BCN_FIFO_TOB_rd_data_count : in STD_LOGIC_VECTOR (31 downto 0); -- occupancy of BCN & L1A FIFO for TOB Readout
87  TOB_FIFO_pFULL_THRESH_ASSERT : out std_logic_vector (8 downto 0);
89  TOB_FIFO_pFULL_THRESH_NEGATE : out std_logic_vector (8 downto 0);
91  TOB_FIFO_DATA_COUNT : in std_logic_vector (31 downto 0);
93  tob_busy_thresh_assert : out STD_LOGIC_VECTOR (8 downto 0); -- TOBs FIFO
95  tob_busy_thresh_negate : out STD_LOGIC_VECTOR (8 downto 0); -- TOBs FIFO
97  XTOB_EG_FIFO_pFULL_THRESH_ASSERT : out std_logic_vector (8 downto 0);
99  XTOB_EG_FIFO_pFULL_THRESH_NEGATE : out std_logic_vector (8 downto 0);
101  XTOB_EG_FIFO_DATA_COUNT : in std_logic_vector (31 downto 0);
103  XTOB_TAU_FIFO_pFULL_THRESH_ASSERT : out std_logic_vector (8 downto 0);
105  XTOB_TAU_FIFO_pFULL_THRESH_NEGATE : out std_logic_vector (8 downto 0);
107  XTOB_TAU_FIFO_DATA_COUNT : in std_logic_vector (31 downto 0);
109  TOB_Link_output_FIFO_pFULL_THRESH_ASSERT : out std_logic_vector (12 downto 0);
111  TOB_Link_output_FIFO_pFULL_THRESH_NEGATE : out std_logic_vector (12 downto 0);
113  TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT : in std_logic_vector (31 downto 0);
115  TOB_data_FIFO_flags : in std_logic_vector (31 downto 0);
117  SPY_TOB_mem_wr_addr : in std_logic_vector (10 downto 0);
119  ipbus_out_tob_dpram : out ipb_wbus; -- signal going to TOB SPY DPRAM
121  ipbus_in_tob_dpram : in ipb_rbus; -- signal coming from TOB SPY DPRAM
123  tob_fsm_monitor : in std_logic_vector (39 downto 0)
124  );
125 end slave_TOB_readout;
126 
128 architecture Behavioral of slave_TOB_readout is
129  signal ipbw : ipb_wbus_array(N_SLAVES-1 downto 0);
130  signal ipbr, ipbr_d : ipb_rbus_array(N_SLAVES-1 downto 0);
131 
132  signal BCN_in_i : std_logic_vector (31 downto 0);
133  signal TOB_WR_ADDR_OFFSET_REG_i : std_logic_vector (31 downto 0);
134  signal XTOB_EG_WR_ADDR_OFFSET_REG_i : std_logic_vector (31 downto 0);
135  signal XTOB_TAU_WR_ADDR_OFFSET_REG_i : std_logic_vector (31 downto 0);
136  signal TOB_SLICES_TO_RD_i : std_logic_vector (31 downto 0) := X"00000001";
137  signal TOB_FIFO_pFULL_THRESH_ASSERT_i : std_logic_vector (31 downto 0);
138  signal TOB_FIFO_pFULL_THRESH_NEGATE_i : std_logic_vector (31 downto 0);
139  signal TOB_FIFO_DATA_COUNT_i : std_logic_vector (31 downto 0);
140  signal BCN_FIFO_pFULL_THRESH_assert_i : std_logic_vector (31 downto 0);
141  signal BCN_FIFO_pFULL_THRESH_negate_i : std_logic_vector (31 downto 0);
142  signal BCN_FIFO_TOB_rd_data_count_i : std_logic_vector (31 downto 0);
143  signal XTOB_EG_FIFO_pFULL_THRESH_ASSERT_i : std_logic_vector (31 downto 0);
144  signal XTOB_EG_FIFO_pFULL_THRESH_NEGATE_i : std_logic_vector (31 downto 0);
145  signal XTOB_EG_FIFO_DATA_COUNT_i : std_logic_vector (31 downto 0);
146  signal XTOB_TAU_FIFO_pFULL_THRESH_ASSERT_i : std_logic_vector (31 downto 0);
147  signal XTOB_TAU_FIFO_pFULL_THRESH_NEGATE_i : std_logic_vector (31 downto 0);
148  signal XTOB_TAU_FIFO_DATA_COUNT_i : std_logic_vector (31 downto 0);
149  signal TOB_Link_output_FIFO_pFULL_THRESH_ASSERT_i : std_logic_vector (31 downto 0);
150  signal TOB_Link_output_FIFO_pFULL_THRESH_NEGATE_i : std_logic_vector (31 downto 0);
151  signal TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT_i : std_logic_vector (31 downto 0);
152  signal TOB_data_FIFO_flags_i : std_logic_vector (31 downto 0);
153  signal trigger_slice_i : std_logic_vector (31 downto 0);
154  signal tob_busy_thresh_assert_i : STD_LOGIC_VECTOR (31 downto 0) ; -- sorted TOBs_FIFO
155  signal tob_busy_thresh_negate_i : STD_LOGIC_VECTOR (31 downto 0) ; -- sorted TOBs_FIFO
156 
157  signal SPY_TOB_mem_wr_addr_i : std_logic_vector (31 downto 0);
158  signal ipb_strobe_i : std_logic;
159  signal ipb_write_i : std_logic;
160 
161 begin
162  -- input signals
163  BCN_in_i <= X"00000" & BCN_in; -- 12b
164  TOB_FIFO_DATA_COUNT_i <= TOB_FIFO_DATA_COUNT;
165  BCN_FIFO_TOB_rd_data_count_i <= BCN_FIFO_TOB_rd_data_count;
166  XTOB_EG_FIFO_DATA_COUNT_i <= XTOB_EG_FIFO_DATA_COUNT;
167  XTOB_TAU_FIFO_DATA_COUNT_i <= XTOB_TAU_FIFO_DATA_COUNT;
168  TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT_i <= TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT;
169  TOB_data_FIFO_flags_i <= TOB_data_FIFO_flags; -- 32 bits
170  SPY_TOB_mem_wr_addr_i <= X"00000" & "0" & SPY_TOB_mem_wr_addr;
171  -- output signals
172  TOB_WR_ADDR_OFFSET <= TOB_WR_ADDR_OFFSET_REG_i(8 downto 0);
173  XTOB_EG_WR_ADDR_OFFSET <= XTOB_EG_WR_ADDR_OFFSET_REG_i(8 downto 0);
174  XTOB_TAU_WR_ADDR_OFFSET <= XTOB_TAU_WR_ADDR_OFFSET_REG_i(8 downto 0);
175  TOB_SLICES_TO_RD <= TOB_SLICES_TO_RD_i(2 downto 0);
176  trigger_slice <= trigger_slice_i(3 downto 0);
177  TOB_FIFO_pFULL_THRESH_ASSERT <= TOB_FIFO_pFULL_THRESH_ASSERT_i(8 downto 0);
178  TOB_FIFO_pFULL_THRESH_NEGATE <= TOB_FIFO_pFULL_THRESH_NEGATE_i(8 downto 0);
179  XTOB_EG_FIFO_pFULL_THRESH_ASSERT <= XTOB_EG_FIFO_pFULL_THRESH_ASSERT_i(8 downto 0);
180  XTOB_EG_FIFO_pFULL_THRESH_NEGATE <= XTOB_EG_FIFO_pFULL_THRESH_NEGATE_i(8 downto 0);
181  XTOB_TAU_FIFO_pFULL_THRESH_ASSERT <= XTOB_TAU_FIFO_pFULL_THRESH_ASSERT_i(8 downto 0);
182  XTOB_TAU_FIFO_pFULL_THRESH_NEGATE <= XTOB_TAU_FIFO_pFULL_THRESH_NEGATE_i(8 downto 0);
183  TOB_Link_output_FIFO_pFULL_THRESH_ASSERT <= TOB_Link_output_FIFO_pFULL_THRESH_ASSERT_i(12 downto 0);
184  TOB_Link_output_FIFO_pFULL_THRESH_NEGATE <= TOB_Link_output_FIFO_pFULL_THRESH_NEGATE_i(12 downto 0);
185  BCN_FIFO_pFULL_THRESH_assert <= BCN_FIFO_pFULL_THRESH_assert_i(8 downto 0);
186  BCN_FIFO_pFULL_THRESH_negate <= BCN_FIFO_pFULL_THRESH_negate_i(8 downto 0);
187  tob_busy_thresh_assert <= tob_busy_thresh_assert_i(8 downto 0);
188  tob_busy_thresh_negate <= tob_busy_thresh_negate_i(8 downto 0);
189 
190 
191 ---- access to TOB DPRAM spy memeory
192  ipbus_out_tob_dpram <= ipbw(N_SLV_TOB_DATA_SPY_MEM); -- signal going to TOB SPY DPRAM
193  ipbr(N_SLV_TOB_DATA_SPY_MEM) <= ipbus_in_tob_dpram; -- signal coming from TOB SPY DPRAM
194 
195  ipb_strobe_i <= IPb_in.ipb_strobe;
196  ipb_write_i <= IPb_in.ipb_write;
197 
198 --U1_ila_TOB_reg : ila_ipbus_fabric_rd_wr
199 --PORT MAP (
200 -- clk => ipb_clk,
201 -- probe0 => TOB_WR_ADDR_OFFSET_REG_i, -- 32b
202 -- probe1 => XTOB_EG_WR_ADDR_OFFSET_REG_i, -- 32b
203 -- probe2(0) => ipb_strobe_i, -- 1b
204 -- probe3(0) => ipb_write_i, -- 1b
205 -- probe4 => (others => '0'), -- 1b
206 -- probe5 => XTOB_TAU_WR_ADDR_OFFSET_REG_i, -- 32b
207 -- probe6 => (others => '0'), -- 32b
208 -- probe7 => (others => '0') , -- 1b
209 -- probe8 => (others => '0') , -- 1b
210 -- probe9 => (others => '0') -- 1b
211 --);
212 
213 
214 -- The IPBus bus fabric, which also has address select logic and data multiplexers.
215 -- This module selects the addressed slave depending on the state of incoming control lines.
216  TOB_rdout_fabric : entity ipbus_lib.ipbus_fabric_sel
217  generic map(NSLV => N_SLAVES,
218  SEL_WIDTH => ipbus_sel_width)
219  port map(
220  ipb_in => ipb_in,
221  ipb_out => ipb_out,
222  sel => ipbus_sel_efex_tob_readout(ipb_in.ipb_addr),
223  ipb_to_slaves => ipbw,
224  ipb_from_slaves => ipbr
225  );
226 
227 -- The L1A_ID counter after receiving an L1A signal
228  U1_L1A_ID_counter : entity ipbus_lib.ipbus_ctrlreg_v
229  generic map(N_CTRL => 0, N_STAT => 1)
230  port map(
231  clk => ipb_clk,
232  reset => ipb_rst,
233  ipbus_in => ipbw(N_SLV_L1A_COUNTER),
234  ipbus_out => ipbr(N_SLV_L1A_COUNTER),
235  d(0) => L1A_ID, -- read only reg 8b & 24b of L1A counter
236  q => open,
237  stb => open);
238 
239 -- The L1A_ID inserted in event header after receiving an L1A signal
240  U1_L1A_ID_event : entity ipbus_lib.ipbus_ctrlreg_v
241  generic map(N_CTRL => 0, N_STAT => 1)
242  port map(
243  clk => ipb_clk,
244  reset => ipb_rst,
245  ipbus_in => ipbw(N_SLV_L1A_ID_EVENT),
246  ipbus_out => ipbr(N_SLV_L1A_ID_EVENT),
247  d(0) => L1A_ID_Event, -- read only reg 8b & 24b of current event
248  q => open,
249  stb => open);
250 
251 -- The Bunch Crossing Number, changes every clock, reset every orbit with BCR signal
252  U2_BCN_in : entity ipbus_lib.ipbus_ctrlreg_v
253  generic map(N_CTRL => 0, N_STAT => 1)
254  port map(
255  clk => ipb_clk,
256  reset => ipb_rst,
257  ipbus_in => ipbw(N_SLV_BCN),
258  ipbus_out => ipbr(N_SLV_BCN),
259  d(0) => BCN_in_i, -- read only reg
260  q => open,
261  stb => open);
262 
263 -- TOB_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing TOBs
264  U3_TOB_WR_ADDR_OFFSET_REG : entity ipbus_lib.ipbus_ctrlreg_v
265  generic map(N_CTRL => 1, N_STAT => 0)
266  port map(
267  clk => ipb_clk,
268  reset => ipb_rst,
269  ipbus_in => ipbw(N_SLV_TOB_WR_ADDR_OFFSET_REG),
270  ipbus_out => ipbr(N_SLV_TOB_WR_ADDR_OFFSET_REG),
271  q(0) => TOB_WR_ADDR_OFFSET_REG_i, -- read/write reg
272  d => (others => (others => '0')),
273  stb => open);
274 
275 -- XTOB_EG_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing e/g XTOBs
276  U3_XTOB_EG_WR_ADDR_OFFSET_REG : entity ipbus_lib.ipbus_ctrlreg_v
277  generic map(N_CTRL => 1, N_STAT => 0)
278  port map(
279  clk => ipb_clk,
280  reset => ipb_rst,
281  ipbus_in => ipbw(N_SLV_XTOB_EG_WR_ADDR_OFFSET_REG),
282  ipbus_out => ipbr(N_SLV_XTOB_EG_WR_ADDR_OFFSET_REG),
283  q(0) => XTOB_EG_WR_ADDR_OFFSET_REG_i, -- read/write reg
284  d => (others => (others => '0')),
285  stb => open);
286 
287 -- XTOB_TAU_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing tau XTOBs
288  U3_XTOB_TAU_WR_ADDR_OFFSET_REG : entity ipbus_lib.ipbus_ctrlreg_v
289  generic map(N_CTRL => 1, N_STAT => 0)
290  port map(
291  clk => ipb_clk,
292  reset => ipb_rst,
293  ipbus_in => ipbw(N_SLV_XTOB_TAU_WR_ADDR_OFFSET_REG),
294  ipbus_out => ipbr(N_SLV_XTOB_TAU_WR_ADDR_OFFSET_REG),
295  q(0) => XTOB_TAU_WR_ADDR_OFFSET_REG_i, -- read/write reg
296  d => (others => (others => '0')),
297  stb => open);
298 
299 -- TOB_SLICES_TO_RD holds the value for the number of slices to read for every L1A signal
300  U4_TOB_SLICES_TO_RD : entity ipbus_lib.ipbus_ctrlreg_v
301  generic map(N_CTRL => 1, N_STAT => 0)
302  port map(
303  clk => ipb_clk,
304  reset => ipb_rst,
305  ipbus_in => ipbw(N_SLV_TOB_SLICES_TO_RD),
306  ipbus_out => ipbr(N_SLV_TOB_SLICES_TO_RD),
307  q(0) => TOB_SLICES_TO_RD_i, -- read/write reg
308  d => (others => (others => '0')),
309  ctrl_default(0) => X"00000001", -- optional port for non-zero default value
310  stb => open);
311 
312 -- TRIGGER_SLICE holds the value for the trigger slice number (on L1A)
313  U4_trigger_slice : entity ipbus_lib.ipbus_ctrlreg_v
314  generic map(N_CTRL => 1, N_STAT => 0)
315  port map(
316  clk => ipb_clk,
317  reset => ipb_rst,
318  ipbus_in => ipbw(N_SLV_TRIGGER_SLICE),
319  ipbus_out => ipbr(N_SLV_TRIGGER_SLICE),
320  q(0) => trigger_slice_i, -- read/write reg
321  ctrl_default(0) => X"00000000", -- optional port for non-zero default value
322  d => (others => (others => '0')),
323  stb => open);
324 
325 -- TOB_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert
326  U5_TOB_FIFO_pFULL_THRESH_ASSERT : entity ipbus_lib.ipbus_ctrlreg_v
327  generic map(N_CTRL => 1, N_STAT => 0)
328  port map(
329  clk => ipb_clk,
330  reset => ipb_rst,
331  ipbus_in => ipbw(N_SLV_TOB_FIFO_PROG_FULL_THRESH_ASSERT),
332  ipbus_out => ipbr(N_SLV_TOB_FIFO_PROG_FULL_THRESH_ASSERT),
333  q(0) => TOB_FIFO_pFULL_THRESH_ASSERT_i, -- read/write reg
334  ctrl_default(0) => X"00000180", -- optional port for non-zero default value
335  d => (others => (others => '0')),
336  stb => open);
337 
338 -- TOB_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert
339  U6_TOB_FIFO_pFULL_THRESH_NEGATE : entity ipbus_lib.ipbus_ctrlreg_v
340  generic map(N_CTRL => 1, N_STAT => 0)
341  port map(
342  clk => ipb_clk,
343  reset => ipb_rst,
344  ipbus_in => ipbw(N_SLV_TOB_FIFO_PROG_FULL_THRESH_NEGATE),
345  ipbus_out => ipbr(N_SLV_TOB_FIFO_PROG_FULL_THRESH_NEGATE),
346  q(0) => TOB_FIFO_pFULL_THRESH_NEGATE_i, -- read/write reg
347  ctrl_default(0) => X"00000100", -- optional port for non-zero default value
348  d => (others => (others => '0')),
349  stb => open);
350 
351 -- TOB_FIFO_DATA_COUNT holds the number of data words stored in the TOB FIFO
352  U7_TOB_FIFO_DATA_COUNT : entity ipbus_lib.ipbus_ctrlreg_v
353  generic map(N_CTRL => 0, N_STAT => 1)
354  port map(
355  clk => ipb_clk,
356  reset => ipb_rst,
357  ipbus_in => ipbw(N_SLV_TOB_FIFO_DATA_COUNT),
358  ipbus_out => ipbr(N_SLV_TOB_FIFO_DATA_COUNT),
359  d(0) => TOB_FIFO_DATA_COUNT_i, -- read only reg
360  q => open,
361  stb => open);
362 
363 -- TOB BUSY flag assertion level
364 U7_TOB_BUSY_THRESH_ASSERT : entity ipbus_lib.ipbus_ctrlreg_v
365  generic map (
366  N_CTRL => 1, --number of control reg
367  N_STAT => 0) --number of status reg
368  port map (
369  clk => ipb_clk,
370  reset => ipb_rst,
371  ipbus_in => ipbw(N_SLV_TOB_BUSY_THRESH_ASSERT),
372  ipbus_out => ipbr(N_SLV_TOB_BUSY_THRESH_ASSERT),
373  d => (others=> (others=> '0')),
374  ctrl_default(0) => X"00000160", -- optional port for non-zero default value
375  q(0) => (tob_busy_thresh_assert_i),
376  stb => open
377  );
378 
379 -- TOB BUSY flag negation level
380 U7_TOB_BUSY_THRESH_NEGATE : entity ipbus_lib.ipbus_ctrlreg_v
381  generic map (
382  N_CTRL => 1, --number of control reg
383  N_STAT => 0) --number of status reg
384  port map (
385  clk => ipb_clk,
386  reset => ipb_rst,
387  ipbus_in => ipbw(N_SLV_TOB_BUSY_THRESH_NEGATE),
388  ipbus_out => ipbr(N_SLV_TOB_BUSY_THRESH_NEGATE),
389  d => (others=> (others=> '0')),
390  ctrl_default(0) => X"00000100", -- optional port for non-zero default value
391  q(0) => (tob_busy_thresh_negate_i),
392  stb => open
393  );
394 
395 -- BCN & L1A FIFO occupancy for TOB Readout
396  U7_BCN_FIFO_TOB_rd_data_count : entity ipbus_lib.ipbus_ctrlreg_v
397  generic map(N_CTRL => 0, N_STAT => 1)
398  port map(
399  clk => ipb_clk,
400  reset => ipb_rst,
401  ipbus_in => ipbw(N_SLV_BCN_FIFO_TOB_RD_DATA_COUNT),
402  ipbus_out => ipbr(N_SLV_BCN_FIFO_TOB_RD_DATA_COUNT),
403  d(0) => BCN_FIFO_TOB_rd_data_count_i, -- read only reg
404  q => open,
405  stb => open);
406 
407 -- XTOB_EG_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert
408  U8_XTOB_EG_FIFO_pFULL_THRESH_ASSERT : entity ipbus_lib.ipbus_ctrlreg_v
409  generic map(N_CTRL => 1, N_STAT => 0)
410  port map(
411  clk => ipb_clk,
412  reset => ipb_rst,
413  ipbus_in => ipbw(N_SLV_XTOB_EG_FIFO_PROG_FULL_THRESH_ASSERT),
414  ipbus_out => ipbr(N_SLV_XTOB_EG_FIFO_PROG_FULL_THRESH_ASSERT),
415  q(0) => XTOB_EG_FIFO_pFULL_THRESH_ASSERT_i, -- read/write reg
416  ctrl_default(0) => X"00000180", -- optional port for non-zero default value
417  d => (others => (others => '0')),
418  stb => open);
419 
420 -- XTOB_EG_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert
421  U9_XTOB_EG_FIFO_pFULL_THRESH_NEGATE : entity ipbus_lib.ipbus_ctrlreg_v
422  generic map(N_CTRL => 1, N_STAT => 0)
423  port map(
424  clk => ipb_clk,
425  reset => ipb_rst,
426  ipbus_in => ipbw(N_SLV_XTOB_EG_FIFO_PROG_FULL_THRESH_NEGATE),
427  ipbus_out => ipbr(N_SLV_XTOB_EG_FIFO_PROG_FULL_THRESH_NEGATE),
428  q(0) => XTOB_EG_FIFO_pFULL_THRESH_NEGATE_i, -- read/write reg
429  ctrl_default(0) => X"00000100", -- optional port for non-zero default value
430  d => (others => (others => '0')),
431  stb => open);
432 
433 -- XTOB_EG_FIFO_DATA_COUNT holds the number of data words stored in the e/g XTOB FIFO
434  U10_XTOB_EG_FIFO_DATA_COUNT : entity ipbus_lib.ipbus_ctrlreg_v
435  generic map(N_CTRL => 0, N_STAT => 1)
436  port map(
437  clk => ipb_clk,
438  reset => ipb_rst,
439  ipbus_in => ipbw(N_SLV_XTOB_EG_FIFO_DATA_COUNT),
440  ipbus_out => ipbr(N_SLV_XTOB_EG_FIFO_DATA_COUNT),
441  d(0) => XTOB_EG_FIFO_DATA_COUNT_i, -- read only reg
442  q => open,
443  stb => open);
444 
445 -- XTOB_TAU_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert
446  U8_XTOB_TAU_FIFO_pFULL_THRESH_ASSERT : entity ipbus_lib.ipbus_ctrlreg_v
447  generic map(N_CTRL => 1, N_STAT => 0)
448  port map(
449  clk => ipb_clk,
450  reset => ipb_rst,
451  ipbus_in => ipbw(N_SLV_XTOB_TAU_FIFO_PROG_FULL_THRESH_ASSERT),
452  ipbus_out => ipbr(N_SLV_XTOB_TAU_FIFO_PROG_FULL_THRESH_ASSERT),
453  q(0) => XTOB_TAU_FIFO_pFULL_THRESH_ASSERT_i, -- read/write reg
454  ctrl_default(0) => X"00000180", -- optional port for non-zero default value
455  d => (others => (others => '0')),
456  stb => open);
457 
458 -- XTOB_TAU_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert
459  U9_XTOB_TAU_FIFO_pFULL_THRESH_NEGATE : entity ipbus_lib.ipbus_ctrlreg_v
460  generic map(N_CTRL => 1, N_STAT => 0)
461  port map(
462  clk => ipb_clk,
463  reset => ipb_rst,
464  ipbus_in => ipbw(N_SLV_XTOB_TAU_FIFO_PROG_FULL_THRESH_NEGATE),
465  ipbus_out => ipbr(N_SLV_XTOB_TAU_FIFO_PROG_FULL_THRESH_NEGATE),
466  q(0) => XTOB_TAU_FIFO_pFULL_THRESH_NEGATE_i, -- read/write reg
467  ctrl_default(0) => X"00000100", -- optional port for non-zero default value
468  d => (others => (others => '0')),
469  stb => open);
470 
471 -- XTOB_TAU_FIFO_DATA_COUNT holds the number of data words stored in the tau XTOB FIFO
472  U10_XTOB_TAU_FIFO_DATA_COUNT : entity ipbus_lib.ipbus_ctrlreg_v
473  generic map(N_CTRL => 0, N_STAT => 1)
474  port map(
475  clk => ipb_clk,
476  reset => ipb_rst,
477  ipbus_in => ipbw(N_SLV_XTOB_TAU_FIFO_DATA_COUNT),
478  ipbus_out => ipbr(N_SLV_XTOB_TAU_FIFO_DATA_COUNT),
479  d(0) => XTOB_TAU_FIFO_DATA_COUNT_i, -- read only reg
480  q => open,
481  stb => open);
482 
483 -- LINK_OUTPUT_FIFO_pFULL_THRESH_ASSERT holds the value for partial full threshold assert of Link Output FIFO
484  U11_LINK_OUTPUT_FIFO_pFULL_THRESH_ASSERT : entity ipbus_lib.ipbus_ctrlreg_v
485  generic map(N_CTRL => 1, N_STAT => 0)
486  port map(
487  clk => ipb_clk,
488  reset => ipb_rst,
489  ipbus_in => ipbw(N_SLV_LINK_OUTPUT_FIFO_PROG_FULL_THRESH_ASSERT),
490  ipbus_out => ipbr(N_SLV_LINK_OUTPUT_FIFO_PROG_FULL_THRESH_ASSERT),
491  q(0) => TOB_LINK_OUTPUT_FIFO_pFULL_THRESH_ASSERT_i, -- read/write reg
492  ctrl_default(0) => X"00001800", -- optional port for non-zero default value
493  d => (others => (others => '0')),
494  stb => open);
495 
496 -- LINK_OUTPUT_FIFO_pFULL_THRESH_NEGATE holds the value for partial full threshold de-assert of Link Output FIFO
497  U12_LINK_OUTPUT_FIFO_pFULL_THRESH_NEGATE : entity ipbus_lib.ipbus_ctrlreg_v
498  generic map(N_CTRL => 1, N_STAT => 0)
499  port map(
500  clk => ipb_clk,
501  reset => ipb_rst,
502  ipbus_in => ipbw(N_SLV_LINK_OUTPUT_FIFO_PROG_FULL_THRESH_NEGATE),
503  ipbus_out => ipbr(N_SLV_LINK_OUTPUT_FIFO_PROG_FULL_THRESH_NEGATE),
504  q(0) => TOB_LINK_OUTPUT_FIFO_pFULL_THRESH_NEGATE_i, -- read/write reg
505  ctrl_default(0) => X"00001000", -- optional port for non-zero default value
506  d => (others => (others => '0')),
507  stb => open);
508 
509 -- LINK_OUTPUT_FIFO_RD_DATA_COUNT holds the number of data words stored in the Link Output FIFO
510  U13_LINK_OUTPUT_FIFO_RD_DATA_COUNT : entity ipbus_lib.ipbus_ctrlreg_v
511  generic map(N_CTRL => 0, N_STAT => 1)
512  port map(
513  clk => ipb_clk,
514  reset => ipb_rst,
515  ipbus_in => ipbw(N_SLV_LINK_OUTPUT_FIFO_RD_DATA_COUNT),
516  ipbus_out => ipbr(N_SLV_LINK_OUTPUT_FIFO_RD_DATA_COUNT),
517  d(0) => TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT_i, -- read only reg
518  q => open,
519  stb => open);
520 
521 -- TOB_data_FIFO_flags holds the status flags for TOB and XTOB FIFOs
522  U12_TOB_data_FIFO_flags : entity ipbus_lib.ipbus_ctrlreg_v
523  generic map(N_CTRL => 0, N_STAT => 1)
524  port map(
525  clk => ipb_clk,
526  reset => ipb_rst,
527  ipbus_in => ipbw(N_SLV_TOB_DATA_FIFO_FLAGS),
528  ipbus_out => ipbr(N_SLV_TOB_DATA_FIFO_FLAGS),
529  d(0) => TOB_data_FIFO_flags_i, -- read only reg
530  q => open,
531  stb => open);
532 
533 -- SPY_TOB_MEM_WR_ADDR holds the current write address for TOB SPY Memory
534  U16_TOB_mem_wr_addr : entity ipbus_lib.ipbus_ctrlreg_v
535  generic map(N_CTRL => 0, N_STAT => 1)
536  port map(
537  clk => ipb_clk,
538  reset => ipb_rst,
539  ipbus_in => ipbw(N_SLV_SPY_TOB_MEM_WR_ADDR),
540  ipbus_out => ipbr(N_SLV_SPY_TOB_MEM_WR_ADDR),
541  d(0) => SPY_TOB_mem_wr_addr_i, -- read only reg
542  q => open,
543  stb => open);
544 
545  U17_BCN_FIFO_pFULL_THRESH_assert : entity ipbus_lib.ipbus_ctrlreg_v
546  generic map(N_CTRL => 1, N_STAT => 0)
547  port map(
548  clk => ipb_clk,
549  reset => ipb_rst,
550  ipbus_in => ipbw(N_SLV_BCN_FIFO_TOB_PFULL_THRESH_ASSERT),
551  ipbus_out => ipbr(N_SLV_BCN_FIFO_TOB_PFULL_THRESH_ASSERT),
552  d => (others => (others => '0')),
553  q(0) => BCN_FIFO_pFULL_THRESH_assert_i, -- read/write reg
554  ctrl_default(0) => X"00000180", -- optional port for non-zero default value
555  stb => open);
556 
557  U18_BCN_FIFO_pFULL_THRESH_negate : entity ipbus_lib.ipbus_ctrlreg_v
558  generic map(N_CTRL => 1, N_STAT => 0)
559  port map(
560  clk => ipb_clk,
561  reset => ipb_rst,
562  ipbus_in => ipbw(N_SLV_BCN_FIFO_TOB_PFULL_THRESH_NEGATE),
563  ipbus_out => ipbr(N_SLV_BCN_FIFO_TOB_PFULL_THRESH_NEGATE),
564  d => (others => (others => '0')),
565  q(0) => BCN_FIFO_pFULL_THRESH_negate_i, -- read/write reg
566  ctrl_default(0) => X"00000100", -- optional port for non-zero default value
567  stb => open);
568 
569 
570 
571 U19_tob_fsm_monitor : entity ipbus_lib.ipbus_ctrlreg_v
572  generic map (
573  N_CTRL => 0, --number of control reg
574  N_STAT => 5) --number of status reg
575  port map (
576  clk => ipb_clk,
577  reset => ipb_rst,
578  ipbus_in => ipbw(N_SLV_TOB_FSM_MONITOR),
579  ipbus_out => ipbr(N_SLV_TOB_FSM_MONITOR),
580  d(0) => X"000000" & tob_fsm_monitor (7 downto 0), -- tob_data_dpram_fsm
581  d(1) => X"000000" & tob_fsm_monitor (15 downto 8), -- xtob_eg_data_dpram_fsm
582  d(2) => X"000000" & tob_fsm_monitor (23 downto 16), -- xtob_tau_data_dpram_fsm
583  d(3) => X"000000" & tob_fsm_monitor (31 downto 24), -- tob_data_mux_fsm
584  d(4) => X"000000" & tob_fsm_monitor (39 downto 32), -- tob_data_mgt_fsm
585  q => open,
586  stb => open
587  );
588 
589 end Behavioral;
TOB_rdout_ip_pkg
Definition: TOB_rdout_ip_pkg.vhd:34
data_type_pkg
Definition: data_type_pkg.vhd:34
slave_TOB_readout.Behavioral
TOB/XTOB data readout slave registers.
Definition: slave_TOB_readout.vhd:128
slave_TOB_readout
TOB/XTOB data readout slave registers.
Definition: slave_TOB_readout.vhd:54
slave_TOB_readout.ipbus_in_tob_dpram
in ipbus_in_tob_dpram ipb_rbus
IPBus signal coming from TOB/XTOB SPY DPRAM.
Definition: slave_TOB_readout.vhd:121
slave_TOB_readout.TOB_WR_ADDR_OFFSET
out TOB_WR_ADDR_OFFSET std_logic_vector( 8 downto 0)
The write address offset pre load for TOB Circular DRPAM.
Definition: slave_TOB_readout.vhd:71
slave_TOB_readout.TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT
in TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT std_logic_vector( 31 downto 0)
Link output FIFO (before MGT) occupancy data count.
Definition: slave_TOB_readout.vhd:113
slave_TOB_readout.trigger_slice
out trigger_slice STD_LOGIC_VECTOR( 3 downto 0)
Trigger slice number - on L1A.
Definition: slave_TOB_readout.vhd:79
slave_TOB_readout.TOB_SLICES_TO_RD
out TOB_SLICES_TO_RD std_logic_vector( 2 downto 0)
number of DRP locations (Slices) to read 1 to 5
Definition: slave_TOB_readout.vhd:77
slave_TOB_readout.ipb_rst
in ipb_rst std_logic
IPBus Reset input.
Definition: slave_TOB_readout.vhd:57
slave_TOB_readout.TOB_Link_output_FIFO_pFULL_THRESH_ASSERT
out TOB_Link_output_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 12 downto 0)
Link output FIFO (before MGT) partial full flag assert threshold.
Definition: slave_TOB_readout.vhd:109
slave_TOB_readout.tob_busy_thresh_assert
out tob_busy_thresh_assert STD_LOGIC_VECTOR( 8 downto 0)
sorted TOB BUSY flag threshold assert
Definition: slave_TOB_readout.vhd:93
slave_TOB_readout.XTOB_TAU_WR_ADDR_OFFSET
out XTOB_TAU_WR_ADDR_OFFSET std_logic_vector( 8 downto 0)
The write address offset pre load for XTOB tau Circular DRPAM.
Definition: slave_TOB_readout.vhd:75
slave_TOB_readout.XTOB_EG_FIFO_DATA_COUNT
in XTOB_EG_FIFO_DATA_COUNT std_logic_vector( 31 downto 0)
XTOB e/g Derandomisation FIFO FIFO occupancy data count.
Definition: slave_TOB_readout.vhd:101
slave_TOB_readout.TOB_FIFO_pFULL_THRESH_NEGATE
out TOB_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 8 downto 0)
TOB Derandomisation FIFO partial full flag negate threshold.
Definition: slave_TOB_readout.vhd:89
slave_TOB_readout.XTOB_EG_FIFO_pFULL_THRESH_NEGATE
out XTOB_EG_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 8 downto 0)
XTOB e/g Derandomisation FIFO partial full flag negate threshold.
Definition: slave_TOB_readout.vhd:99
slave_TOB_readout.IPb_out
out IPb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: slave_TOB_readout.vhd:63
slave_TOB_readout.XTOB_EG_FIFO_pFULL_THRESH_ASSERT
out XTOB_EG_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 8 downto 0)
XTOB e/g Derandomisation FIFO partial full flag assert threshold.
Definition: slave_TOB_readout.vhd:97
slave_TOB_readout.XTOB_TAU_FIFO_pFULL_THRESH_ASSERT
out XTOB_TAU_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 8 downto 0)
XTOB tau Derandomisation FIFO partial full flag assert threshold.
Definition: slave_TOB_readout.vhd:103
slave_TOB_readout.TOB_Link_output_FIFO_pFULL_THRESH_NEGATE
out TOB_Link_output_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 12 downto 0)
Link output FIFO (before MGT) partial full flag negate threshold.
Definition: slave_TOB_readout.vhd:111
slave_TOB_readout.L1A_ID
in L1A_ID std_logic_vector( 31 downto 0)
8b Extended L1A ID + 24b L1A ID of counter
Definition: slave_TOB_readout.vhd:67
slave_TOB_readout.XTOB_TAU_FIFO_pFULL_THRESH_NEGATE
out XTOB_TAU_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 8 downto 0)
XTOB tau Derandomisation FIFO partial full flag negate threshold.
Definition: slave_TOB_readout.vhd:105
slave_TOB_readout.TOB_FIFO_DATA_COUNT
in TOB_FIFO_DATA_COUNT std_logic_vector( 31 downto 0)
TOB Derandomisation FIFO FIFO occupancy data count.
Definition: slave_TOB_readout.vhd:91
slave_TOB_readout.IPb_in
in IPb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: slave_TOB_readout.vhd:61
slave_TOB_readout.ipb_clk
in ipb_clk std_logic
IPBus Clock input.
Definition: slave_TOB_readout.vhd:59
slave_TOB_readout.XTOB_TAU_FIFO_DATA_COUNT
in XTOB_TAU_FIFO_DATA_COUNT std_logic_vector( 31 downto 0)
XTOB tau Derandomisation FIFO FIFO occupancy data count.
Definition: slave_TOB_readout.vhd:107
slave_TOB_readout.SPY_TOB_mem_wr_addr
in SPY_TOB_mem_wr_addr std_logic_vector( 10 downto 0)
TOB/XTOB SPY Memory write address (read only register)
Definition: slave_TOB_readout.vhd:117
slave_TOB_readout.ipbus_out_tob_dpram
out ipbus_out_tob_dpram ipb_wbus
IPBus signal going to TOB/XTOB SPY DPRAM.
Definition: slave_TOB_readout.vhd:119
slave_TOB_readout.TOB_FIFO_pFULL_THRESH_ASSERT
out TOB_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 8 downto 0)
TOB Derandomisation FIFO partial full flag assert threshold.
Definition: slave_TOB_readout.vhd:87
slave_TOB_readout.tob_fsm_monitor
in tob_fsm_monitor std_logic_vector( 39 downto 0)
Monitor TOB Readout state machines.
Definition: slave_TOB_readout.vhd:124
slave_TOB_readout.BCN_FIFO_TOB_rd_data_count
in BCN_FIFO_TOB_rd_data_count STD_LOGIC_VECTOR( 31 downto 0)
BCN & L1A FIFO occupancy for TOB Readout.
Definition: slave_TOB_readout.vhd:85
slave_TOB_readout.tob_busy_thresh_negate
out tob_busy_thresh_negate STD_LOGIC_VECTOR( 8 downto 0)
sorted TOB BUSY flag threshold de-assert
Definition: slave_TOB_readout.vhd:95
slave_TOB_readout.TOB_data_FIFO_flags
in TOB_data_FIFO_flags std_logic_vector( 31 downto 0)
Read only register containing all Empty pFull and Full of TOB/XTOB data block.
Definition: slave_TOB_readout.vhd:115
slave_TOB_readout.XTOB_EG_WR_ADDR_OFFSET
out XTOB_EG_WR_ADDR_OFFSET std_logic_vector( 8 downto 0)
The write address offset pre load for XTOB e/g Circular DRPAM.
Definition: slave_TOB_readout.vhd:73
slave_TOB_readout.L1A_ID_Event
in L1A_ID_Event std_logic_vector( 31 downto 0)
8b Ext L1A ID from TTC input + 24b L1A ID of counter from TTC FIFO - inserted in the event header
Definition: slave_TOB_readout.vhd:65
slave_TOB_readout.BCN_FIFO_pFULL_THRESH_negate
out BCN_FIFO_pFULL_THRESH_negate std_logic_vector( 8 downto 0)
BCN FIFO partial full flag negate threshold.
Definition: slave_TOB_readout.vhd:83
slave_TOB_readout.BCN_FIFO_pFULL_THRESH_assert
out BCN_FIFO_pFULL_THRESH_assert std_logic_vector( 8 downto 0)
BCN FIFO partial full flag assert threshold.
Definition: slave_TOB_readout.vhd:81
slave_TOB_readout.BCN_in
in BCN_in std_logic_vector( 11 downto 0)
Bunch Crossing number input.
Definition: slave_TOB_readout.vhd:69
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