slave_TOB_readout Entity Reference

TOB/XTOB data readout slave registers. More...

Inheritance diagram for slave_TOB_readout:

Entities
Behavioral	architecture
	TOB/XTOB data readout slave registers. More...

Libraries
IEEE
ipbus_lib
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
ipbus
data_type_pkg	Package <data_type_pkg>
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
ipbus_decode_efex_tob_readout

Ports
ipb_rst	in	std_logic
		IPBus Reset input.
ipb_clk	in	std_logic
		IPBus Clock input.
IPb_in	in	ipb_wbus
		IPBus input bus going from master to slaves.
IPb_out	out	ipb_rbus
		IPBus output bus going from slaves to master.
L1A_ID_Event	in	std_logic_vector ( 31 downto 0 )
		8b Ext L1A ID from TTC input + 24b L1A ID of counter from TTC FIFO - inserted in the event header
L1A_ID	in	std_logic_vector ( 31 downto 0 )
		8b Extended L1A ID + 24b L1A ID of counter
BCN_in	in	std_logic_vector ( 11 downto 0 )
		Bunch Crossing number input.
TOB_WR_ADDR_OFFSET	out	std_logic_vector ( 8 downto 0 )
		The write address offset pre load for TOB Circular DRPAM.
XTOB_EG_WR_ADDR_OFFSET	out	std_logic_vector ( 8 downto 0 )
		The write address offset pre load for XTOB e/g Circular DRPAM.
XTOB_TAU_WR_ADDR_OFFSET	out	std_logic_vector ( 8 downto 0 )
		The write address offset pre load for XTOB tau Circular DRPAM.
TOB_SLICES_TO_RD	out	std_logic_vector ( 2 downto 0 )
		number of DRP locations (Slices) to read 1 to 5
trigger_slice	out	STD_LOGIC_VECTOR ( 3 downto 0 )
		Trigger slice number - on L1A.
BCN_FIFO_pFULL_THRESH_assert	out	std_logic_vector ( 8 downto 0 )
		BCN FIFO partial full flag assert threshold.
BCN_FIFO_pFULL_THRESH_negate	out	std_logic_vector ( 8 downto 0 )
		BCN FIFO partial full flag negate threshold.
BCN_FIFO_TOB_rd_data_count	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		BCN & L1A FIFO occupancy for TOB Readout.
TOB_FIFO_pFULL_THRESH_ASSERT	out	std_logic_vector ( 8 downto 0 )
		TOB Derandomisation FIFO partial full flag assert threshold.
TOB_FIFO_pFULL_THRESH_NEGATE	out	std_logic_vector ( 8 downto 0 )
		TOB Derandomisation FIFO partial full flag negate threshold.
TOB_FIFO_DATA_COUNT	in	std_logic_vector ( 31 downto 0 )
		TOB Derandomisation FIFO FIFO occupancy data count.
tob_busy_thresh_assert	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		sorted TOB BUSY flag threshold assert
tob_busy_thresh_negate	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		sorted TOB BUSY flag threshold de-assert
XTOB_EG_FIFO_pFULL_THRESH_ASSERT	out	std_logic_vector ( 8 downto 0 )
		XTOB e/g Derandomisation FIFO partial full flag assert threshold.
XTOB_EG_FIFO_pFULL_THRESH_NEGATE	out	std_logic_vector ( 8 downto 0 )
		XTOB e/g Derandomisation FIFO partial full flag negate threshold.
XTOB_EG_FIFO_DATA_COUNT	in	std_logic_vector ( 31 downto 0 )
		XTOB e/g Derandomisation FIFO FIFO occupancy data count.
XTOB_TAU_FIFO_pFULL_THRESH_ASSERT	out	std_logic_vector ( 8 downto 0 )
		XTOB tau Derandomisation FIFO partial full flag assert threshold.
XTOB_TAU_FIFO_pFULL_THRESH_NEGATE	out	std_logic_vector ( 8 downto 0 )
		XTOB tau Derandomisation FIFO partial full flag negate threshold.
XTOB_TAU_FIFO_DATA_COUNT	in	std_logic_vector ( 31 downto 0 )
		XTOB tau Derandomisation FIFO FIFO occupancy data count.
TOB_Link_output_FIFO_pFULL_THRESH_ASSERT	out	std_logic_vector ( 12 downto 0 )
		Link output FIFO (before MGT) partial full flag assert threshold.
TOB_Link_output_FIFO_pFULL_THRESH_NEGATE	out	std_logic_vector ( 12 downto 0 )
		Link output FIFO (before MGT) partial full flag negate threshold.
TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT	in	std_logic_vector ( 31 downto 0 )
		Link output FIFO (before MGT) occupancy data count.
TOB_data_FIFO_flags	in	std_logic_vector ( 31 downto 0 )
		Read only register containing all Empty pFull and Full of TOB/XTOB data block.
SPY_TOB_mem_wr_addr	in	std_logic_vector ( 10 downto 0 )
		TOB/XTOB SPY Memory write address (read only register)
ipbus_out_tob_dpram	out	ipb_wbus
		IPBus signal going to TOB/XTOB SPY DPRAM.
ipbus_in_tob_dpram	in	ipb_rbus
		IPBus signal coming from TOB/XTOB SPY DPRAM.
tob_fsm_monitor	in	std_logic_vector ( 39 downto 0 )
		Monitor TOB Readout state machines.

Detailed Description

TOB/XTOB data readout slave registers.

This module provides IPBus access for all Read Only and Read/Write reigster withing the TOB/XTOB data readout block. Function of modules/registers are listed in the same order as VHDL code.

The IPBus bus fabric, which also has address select logic and data multiplexers. This version selects the addressed slave depending on the state of incoming control lines.

• The L1A_ID counter after receiving an L1A signal.
• The L1A_ID inserted in event header after receiving an L1A signal.
• The Bunch Crossing Number, changes every clock, reset every orbit with BCR signal.
• TOB_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing TOBs
• XTOB_EG_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing e/g XTOBs
• XTOB_TAU_WR_ADDR_OFFSET_REG contains the offset value between Read and Write address of Scrolling Dual Port RAM storing tau XTOBs
• TOB_SLICES_TO_RD holds the value for the number of slices to read for every L1A signal.
• TRIGGER_SLICE holds the value of the Trigger slice number - on L1A.
• TOB_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert.
• TOB_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert.
• TOB_FIFO_DATA_COUNT holds the number of data words stored in the TOB FIFO.
• XTOB_EG_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert.
• XTOB_EG_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert.
• XTOB_EG_FIFO_DATA_COUNT holds the number of data words stored in the e/g XTOB FIFO.
• XTOB_TAU_FIFO_PROG_FULL_THRESH_ASSERT holds the value for partial full threshold assert.
• XTOB_TAU_FIFO_PROG_FULL_THRESH_NEGATE holds the value for partial full threshold de-assert.
• XTOB_TAU_FIFO_DATA_COUNT holds the number of data words stored in the tau XTOB FIFO.
• LINK_OUTPUT_FIFO_pFULL_THRESH_ASSERT holds the value for partial full threshold assert of Link Output FIFO.
• LINK_OUTPUT_FIFO_pFULL_THRESH_NEGATE holds the value for partial full threshold de-assert of Link Output FIFO.
• LINK_OUTPUT_FIFO_RD_DATA_COUNT holds the number of data words stored in the Link Output FIFO.
• TOB_data_FIFO_flags holds the status flags for BCN, TOB and XTOB FIFOs as well as Safe Mode Operation.
• SPY_TOB_MEM_WR_ADDR holds the current write address for TOB SPY Memory.
• tob_data_spy_mem: spy RAM (2K) for TOB/XTOB data to cFPGA

The TRIGGER_SLICE register is used to correctly address the DPRAM scrolling memory. In a multi-slice readout, the Read Address of DPRAM, is generated from the Write Address minus the TRIGGER_SLICE so if the TRIGGER_SLICE is the middle slice of a 3 slices readout, the first slice to be read, is the slice before the L1A, then the slice at L1A, and last slice is the slice after L1A.

Author

Saeed Taghavi

Definition at line 54 of file slave_TOB_readout.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/slave_TOB_readout.vhd