clk_closs_pulse_fsm.vhd File Reference

This module accepts an input signal and generate a pulse for clock domain crossing. More...

Go to the source code of this file.

Entities
clk_closs_pulse_fsm	entity
Behavioral	architecture

Detailed Description

This module accepts an input signal and generate a pulse for clock domain crossing.

A 1 tick pulse on input pulse_src causes a toggle flip flop in source domain. The toggle flip flop in destination domain then causes a 1 tick pulse on the output pulse_dest.

Author

Saeed Taghavi

Definition in file clk_closs_pulse_fsm.vhd.