Behavioral Architecture Reference

Processes
u0_tff_clk_src	( clk_src )
u1_tff_clk_dest	( clk_dest )
u2_pulse_clk_dest	( clk_dest )

Signals
last_pulse_src	std_logic := ' 0 '
tff_src	std_logic := ' 0 '
last_pulse_dest	std_logic := ' 0 '
true_pulse_dest	std_logic := ' 0 '
tff_dest	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )

Attributes
ASYNC_REG	string
ASYNC_REG	signal is " TRUE "

Detailed Description

Definition at line 24 of file clk_closs_pulse_fsm.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/clk_closs_pulse_fsm.vhd