clk_closs_pulse_fsm.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity clk_closs_pulse_fsm is
    Port (
    clk_src:    in std_logic;
    rst_src:    in std_logic;
    pulse_src:  in std_logic;
    --
    clk_dest:   in std_logic;
    pulse_dest: out std_logic
           );
end clk_closs_pulse_fsm;
 
architecture Behavioral of clk_closs_pulse_fsm is
 
    signal last_pulse_src: std_logic := '0'; -- signal to ensure pulse only on rising edge of incoming pulse_src
    signal tff_src: std_logic := '0'; -- signal from source that crosses the clock domains
    signal last_pulse_dest, true_pulse_dest: std_logic := '0'; -- signals to ensure single tick pulse on outgoing pulse_dest
    signal tff_dest: std_logic_vector(2 downto 0) := (Others => '0'); -- async register to capture in destination
 
    attribute ASYNC_REG: string;
    attribute ASYNC_REG of tff_src: signal is "TRUE";
    attribute ASYNC_REG of tff_dest: signal is "TRUE";
 
begin
 
 
u0_tff_clk_src: process(clk_src)
    begin
        if rising_edge(clk_src) then
    -- infer toggle flip flop in source domain
            if rst_src = '1' then
                tff_src <= '0';
            else
                tff_src <= tff_src xor (pulse_src and not last_pulse_src);
            end if;
            last_pulse_src <= pulse_src;
        end if;
    end process u0_tff_clk_src;
 
u1_tff_clk_dest: process(clk_dest)
    begin
        if rising_edge(clk_dest) then
    -- pick up tff from source domain
            tff_dest <= tff_dest(1 downto 0) & tff_src;
        end if;
    end process u1_tff_clk_dest;
 
u2_pulse_clk_dest: process(clk_dest)
    begin
        if rising_edge(clk_dest) then
    -- pulse on the toggle
            true_pulse_dest <= (tff_dest(2) xor tff_dest(1)) and not last_pulse_dest;
            last_pulse_dest <= true_pulse_dest;
        end if;
    end process u2_pulse_clk_dest;
 
pulse_dest <= true_pulse_dest;
 
end Behavioral;