official/Doc/readout__ipb__slave_8vhd_source.html

 library IEEE;

 use IEEE.STD_LOGIC_1164.ALL;


 library ipbus_lib;

 use ipbus_lib.ipbus.all;


 library TOB_rdout_lib;

 use TOB_rdout_lib.data_type_pkg.all;

 use TOB_rdout_lib.TOB_rdout_ip_pkg.all;

 use TOB_rdout_lib.ipbus_decode_efex_readout.all;    -- decoder package


 entity readout_ipb_slave is

     Port  (

         ipb_rst          : in std_logic ;

         ipb_clk          : in std_logic ;

         IPb_in           : in ipb_wbus;      -- The signals going from master to slaves

         IPb_out          : out ipb_rbus;     -- The signals going from slaves to master

         L1A_ID_Event     : in STD_LOGIC_VECTOR (31 downto 0);

         L1A_ID           : in STD_LOGIC_VECTOR (31 downto 0);

         BCN_in           : in STD_LOGIC_VECTOR (11 downto 0);

         TOB_WR_ADDR_OFFSET                  : out STD_LOGIC_VECTOR (8 downto 0);

         XTOB_EG_WR_ADDR_OFFSET              : out STD_LOGIC_VECTOR (8 downto 0);

         XTOB_TAU_WR_ADDR_OFFSET             : out STD_LOGIC_VECTOR (8 downto 0);

         TOB_SLICES_TO_RD                    : out STD_LOGIC_VECTOR (2 downto 0);

         trigger_slice                       : out STD_LOGIC_VECTOR(3 downto 0) ;

         TOB_FIFO_pFULL_THRESH_ASSERT        : out STD_LOGIC_VECTOR (8 downto 0);

         TOB_FIFO_pFULL_THRESH_NEGATE        : out STD_LOGIC_VECTOR (8 downto 0);

         TOB_FIFO_DATA_COUNT                 : in  STD_LOGIC_VECTOR (31 downto 0);

         tob_busy_thresh_assert  : out  STD_LOGIC_VECTOR (8 downto 0);    -- TOBs FIFO

         tob_busy_thresh_negate  : out  STD_LOGIC_VECTOR (8 downto 0);    -- TOBs FIFO

         XTOB_EG_FIFO_pFULL_THRESH_ASSERT    : out STD_LOGIC_VECTOR (8 downto 0);

         XTOB_EG_FIFO_pFULL_THRESH_NEGATE    : out STD_LOGIC_VECTOR (8 downto 0);

         XTOB_EG_FIFO_DATA_COUNT             : in  STD_LOGIC_VECTOR (31 downto 0);

         XTOB_TAU_FIFO_pFULL_THRESH_ASSERT   : out STD_LOGIC_VECTOR (8 downto 0);

         XTOB_TAU_FIFO_pFULL_THRESH_NEGATE   : out STD_LOGIC_VECTOR (8 downto 0);

         XTOB_TAU_FIFO_DATA_COUNT            : in  STD_LOGIC_VECTOR (31 downto 0);

         TOB_Link_output_FIFO_pFULL_THRESH_ASSERT : out STD_LOGIC_VECTOR (12 downto 0);

         TOB_Link_output_FIFO_pFULL_THRESH_NEGATE : out STD_LOGIC_VECTOR (12 downto 0);

         TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT       : in  STD_LOGIC_VECTOR (31 downto 0);

         TOB_data_FIFO_flags                      : in  STD_LOGIC_VECTOR (31 downto 0);

         RAW_WR_ADDR_OFFSET           : out STD_LOGIC_VECTOR (9 downto 0);

         RAW_FIFO_pFULL_THRESH_ASSERT : out STD_LOGIC_VECTOR (8 downto 0);

         RAW_FIFO_pFULL_THRESH_NEGATE : out STD_LOGIC_VECTOR (8 downto 0);

         raw_busy_thresh_assert  : out  STD_LOGIC_VECTOR (8 downto 0);    -- TOBs FIFO

         raw_busy_thresh_negate  : out  STD_LOGIC_VECTOR (8 downto 0);    -- TOBs FIFO

         BCN_FIFO_TOB_pFULL_THRESH_assert : out STD_LOGIC_VECTOR (8 downto 0);

         BCN_FIFO_TOB_pFULL_THRESH_negate : out STD_LOGIC_VECTOR (8 downto 0);

         BCN_FIFO_TOB_rd_data_count         : in STD_LOGIC_VECTOR (31 downto 0);   -- occupancy of BCN & L1A FIFO for TOB Readout

         BCN_FIFO_RAW_pFULL_THRESH_assert : out STD_LOGIC_VECTOR (8 downto 0);

         BCN_FIFO_RAW_pFULL_THRESH_negate : out STD_LOGIC_VECTOR (8 downto 0);

         BCN_FIFO_RAW_rd_data_count         : in STD_LOGIC_VECTOR (31 downto 0);   -- occupancy of BCN & L1A FIFO for RAW Readout

         Link_output_FIFO_RAW_rd_data_count        : in  STD_LOGIC_VECTOR (31 downto 0);    -- occupancy of RAW output link MGT FIFO

         Link_output_FIFO_RAW_pfull_thresh_assert  : out STD_LOGIC_VECTOR (12 downto 0);   -- Link_output_FIFO prog_full

         Link_output_FIFO_RAW_pfull_thresh_negate  : out STD_LOGIC_VECTOR (12 downto 0);   -- Link_output_FIFO prog_full

         RAW_FIFO_FULL_THRESH_ASSERT   : out STD_LOGIC_VECTOR(8 downto 0);

         RAW_FIFO_FULL_THRESH_NEGATE   : out STD_LOGIC_VECTOR(8 downto 0);

         RAW_FIFO_data_count           : in  STD_LOGIC_VECTOR(31 downto 0);

         RAW_frame_count        : in  STD_LOGIC_VECTOR (31 downto 0);

         RAW_data_FIFO_flags    : in STD_LOGIC_VECTOR (31 downto 0);

         SPY_TOB_mem_wr_addr    : in STD_LOGIC_VECTOR (10 downto 0);

         ipbus_out_tob_dpram    : out ipb_wbus;     -- signal going to TOB SPY DPRAM

         ipbus_in_tob_dpram     : in  ipb_rbus;     -- signal coming from TOB SPY DPRAM

         RDOUT_PULSE_REG        : out STD_LOGIC_VECTOR (31 downto 0);

         SPY_RAW_mem_wr_addr    : in STD_LOGIC_VECTOR (10 downto 0);

         ipbus_out_raw_dpram    : out ipb_wbus;     -- signal going to RAW SPY DPRAM

         ipbus_in_raw_dpram     : in  ipb_rbus;     -- signal coming from RAW SPY DPRAM

         TEST_CONTROL_REG       : out  STD_LOGIC_VECTOR (31 downto 0);

        link_error_flags        : in STD_LOGIC_VECTOR (53 downto 0);

        busy_raw_counter     : in STD_LOGIC_VECTOR (31 downto 0);

        busy_tob_counter     : in STD_LOGIC_VECTOR (31 downto 0) ;

        busy_raw_duration_counter     : in STD_LOGIC_VECTOR (31 downto 0);

        busy_tob_duration_counter     : in STD_LOGIC_VECTOR (31 downto 0) ;

        ECR_debug_counter     : in STD_LOGIC_VECTOR (31 downto 0);

        L1A_debug_counter     : in STD_LOGIC_VECTOR (31 downto 0);

        real_time_40m_counter     : in STD_LOGIC_VECTOR (31 downto 0);

        tob_double_word_counter   : in STD_LOGIC_VECTOR (31 downto 0);

        raw_fsm_monitor   : out std_logic_vector (31 downto 0);

        tob_fsm_monitor   : out std_logic_vector (39 downto 0);

        ttc_err_history_debug    : in std_logic_vector(31 downto 0);

        l1a_id_good_debug    : in std_logic_vector(31 downto 0);

        l1a_id_err_debug    : in std_logic_vector(31 downto 0);

        l1a_id_expected_debug    : in std_logic_vector(31 downto 0);

        bcn_err_expected_debug    : in std_logic_vector(31 downto 0);

        l1id_parity_err_cntr_debug    : in std_logic_vector(31 downto 0);

        l1id_mismatch_cntr_debug    : in std_logic_vector(31 downto 0);

        bcn_parity_err_cntr_debug    : in std_logic_vector(31 downto 0);

        bcn_mismatch_cntr_debug    : in std_logic_vector(31 downto 0)

         );

 end readout_ipb_slave;


 architecture Behavioral of readout_ipb_slave is

     signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);

     signal ipbr, ipbr_d: ipb_rbus_array(N_SLAVES-1 downto 0);


     signal RDOUT_PULSE_REG_i  : STD_LOGIC_VECTOR (31 downto 0);

     signal rst_pulse_reg_i    : STD_LOGIC := '0';

     signal rst_pulse_reg_ii   : STD_LOGIC;

     signal IPbw_in_i          : ipb_wbus;     -- The signals going from master to slaves

     signal IPbr_out_i         : ipb_rbus;     -- The signals going from slaves to master

     signal TEST_CONTROL_REG_i : STD_LOGIC_VECTOR (31 downto 0);

     signal rst_ECR_dbg_cntr_i      : STD_LOGIC  := '0' ;

     signal rst_L1A_dbg_cntr_i      : STD_LOGIC  := '0' ;


     signal ipbus_out_raw_dpram_i : ipb_wbus;     -- signal going to RAW SPY DPRAM

     signal ipbus_in_raw_dpram_i  : ipb_rbus;     -- signal coming from RAW SPY DPRAM

     signal ipbus_out_tob_dpram_i : ipb_wbus;     -- signal going to TOB SPY DPRAM

     signal ipbus_in_tob_dpram_i  : ipb_rbus;     -- signal coming from TOB SPY DPRAM


 begin


     -- outputs

     ipb_out             <= IPbr_out_i ;

     RDOUT_PULSE_REG     <= RDOUT_PULSE_REG_i ;

     TEST_CONTROL_REG    <= TEST_CONTROL_REG_i ;


     ipbus_out_raw_dpram  <= ipbus_out_raw_dpram_i ;     -- signal going to RAW SPY DPRAM

     ipbus_in_raw_dpram_i <= ipbus_in_raw_dpram    ;     -- signal coming from RAW SPY DPRAM


     ipbus_out_tob_dpram  <= ipbus_out_tob_dpram_i ;     -- signal going to TOB SPY DPRAM

     ipbus_in_tob_dpram_i <= ipbus_in_tob_dpram    ;     -- signal coming from TOB SPY DPRAM


 -- The IPBus bus fabric, which also has address select logic and data multiplexers.

 -- This version selects the addressed slave depending on the state of incoming control lines.


 U1_rdout_fabric: entity ipbus_lib.ipbus_fabric_sel

     generic map(NSLV => N_SLAVES,

         SEL_WIDTH => ipbus_sel_width)

     port map(

        ipb_in => ipb_in,

        ipb_out => IPbr_out_i,

        sel => ipbus_sel_efex_readout(ipb_in.ipb_addr),

        ipb_to_slaves => ipbw,

        ipb_from_slaves => ipbr

      );


 -- This is 32b register, which is read/written through the IPBus.


 U2_Test_Cntl_Reg : entity ipbus_lib.ipbus_ctrlreg_v

     generic map (

       N_CTRL => 1,                 --number of control reg

       N_STAT => 0)                 --number of status reg

     port map (

       clk       => ipb_clk,

       reset     => ipb_rst,

       ipbus_in  => ipbw(N_SLV_TEST_CONTROL_REG),

       ipbus_out => ipbr(N_SLV_TEST_CONTROL_REG),

       d         => (others=> (others=> '0')),

       ctrl_default(0) => (others=> '0'),    -- optional port for non-zero default value

       q(0)      => (TEST_CONTROL_REG_i),

       stb       => open

       );


 -- This is 32b register, which is read/written through the IPBus.

 -- This is a Pulse Register and automatically resets to ZERO after one clock cycle.


 U3_pulsed_register : entity ipbus_lib.ipbus_ctrlreg_v

     generic map (

       N_CTRL => 1,                 --number of control reg

       N_STAT => 0)                 --number of status reg

     port map (

       clk       => ipb_clk,

       reset     => rst_pulse_reg_ii,    -- ipb_rst,

       ipbus_in  => ipbw(N_SLV_RDOUT_PULSE_REG),

       ipbus_out => ipbr(N_SLV_RDOUT_PULSE_REG),

       d         => (others=> (others=> '0')),

       q(0)      => (RDOUT_PULSE_REG_i),

       stb       => open

       );


     rst_pulse_reg_ii <= rst_pulse_reg_i OR ipb_rst;


 U3_top_level_counters : entity ipbus_lib.ipbus_ctrlreg_v

     generic map (

       N_CTRL => 0,                 --number of control reg

       N_STAT => 8)                 --number of status reg

     port map (

       clk       => ipb_clk,

       reset     => ipb_rst,

       ipbus_in  => ipbw(N_SLV_TOP_LEVEL_COUNTERS),

       ipbus_out => ipbr(N_SLV_TOP_LEVEL_COUNTERS),

       d(0)      => busy_raw_counter,

       d(1)      => busy_tob_counter,

       d(2)      => busy_raw_duration_counter,

       d(3)      => busy_tob_duration_counter,

       d(4)      => ECR_debug_counter,

       d(5)      => L1A_debug_counter,

       d(6)      => real_time_40m_counter,

       d(7)      => tob_double_word_counter,

       q         => open,

       stb       => open

       );


 U3_ttc_parity_L1A_BCN : entity ipbus_lib.ipbus_ctrlreg_v

     generic map (

       N_CTRL => 0,                 --number of control reg

       N_STAT => 9)                 --number of status reg

     port map (

       clk       => ipb_clk,

       reset     => ipb_rst,

       ipbus_in  => ipbw(N_SLV_TTC_PARITY_L1A_BCN),

       ipbus_out => ipbr(N_SLV_TTC_PARITY_L1A_BCN),

       d(0)      => ttc_err_history_debug,

       d(1)      => l1a_id_good_debug,

       d(2)      => l1a_id_err_debug,

       d(3)      => l1a_id_expected_debug,

       d(4)      => bcn_err_expected_debug,

       d(5)      => l1id_parity_err_cntr_debug,

       d(6)      => l1id_mismatch_cntr_debug,

       d(7)      => bcn_parity_err_cntr_debug,

       d(8)      => bcn_mismatch_cntr_debug,

       q         => open,

       stb       => open

       );


 U4_rst_pulse_reg : process (ipb_clk)    -- this generates the reset for pulsed register.

     begin

     if rising_edge(ipb_clk) then

         if RDOUT_PULSE_REG_i /= X"00000000"  then

             rst_pulse_reg_i <= '1';

         else

             rst_pulse_reg_i <= '0';

         end if;

     end if;

 end process;


 -- TOB/XTOB data readout slave registers

 U4_TOB_slave: entity TOB_rdout_lib.slave_TOB_readout

   port map(

      ipb_clk     => ipb_clk,

      ipb_rst     => ipb_rst,

      ipb_in     => ipbw(N_SLV_TOB),

      ipb_out    => ipbr(N_SLV_TOB),

      L1A_ID_Event => L1A_ID_Event,

      L1A_ID     => L1A_ID,

      BCN_in     => BCN_in,

      TOB_WR_ADDR_OFFSET               => TOB_WR_ADDR_OFFSET,

      XTOB_EG_WR_ADDR_OFFSET           => XTOB_EG_WR_ADDR_OFFSET,

      XTOB_TAU_WR_ADDR_OFFSET          => XTOB_TAU_WR_ADDR_OFFSET,

      TOB_SLICES_TO_RD                 => TOB_SLICES_TO_RD,

      trigger_slice                    => trigger_slice,

      BCN_FIFO_TOB_rd_data_count       =>  BCN_FIFO_TOB_rd_data_count ,      -- i/p

      BCN_FIFO_pFULL_THRESH_assert     =>  BCN_FIFO_TOB_pFULL_THRESH_assert ,     -- o/p

      BCN_FIFO_pFULL_THRESH_negate     =>  BCN_FIFO_TOB_pFULL_THRESH_negate ,     -- o/p

      TOB_FIFO_pFULL_THRESH_ASSERT     => TOB_FIFO_pFULL_THRESH_ASSERT,

      TOB_FIFO_pFULL_THRESH_NEGATE     => TOB_FIFO_pFULL_THRESH_NEGATE,

      TOB_FIFO_DATA_COUNT              => TOB_FIFO_DATA_COUNT,

      tob_busy_thresh_assert           =>  tob_busy_thresh_assert, -- i/p

      tob_busy_thresh_negate           =>  tob_busy_thresh_negate, -- i/p

      XTOB_EG_FIFO_pFULL_THRESH_ASSERT => XTOB_EG_FIFO_pFULL_THRESH_ASSERT,

      XTOB_EG_FIFO_pFULL_THRESH_NEGATE => XTOB_EG_FIFO_pFULL_THRESH_NEGATE,

      XTOB_EG_FIFO_DATA_COUNT          => XTOB_EG_FIFO_DATA_COUNT,

      XTOB_TAU_FIFO_pFULL_THRESH_ASSERT => XTOB_TAU_FIFO_pFULL_THRESH_ASSERT,

      XTOB_TAU_FIFO_pFULL_THRESH_NEGATE => XTOB_TAU_FIFO_pFULL_THRESH_NEGATE,

      XTOB_TAU_FIFO_DATA_COUNT         => XTOB_TAU_FIFO_DATA_COUNT,

      TOB_Link_output_FIFO_pFULL_THRESH_ASSERT => TOB_Link_output_FIFO_pFULL_THRESH_ASSERT,

      TOB_Link_output_FIFO_pFULL_THRESH_NEGATE => TOB_Link_output_FIFO_pFULL_THRESH_NEGATE,

      TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT      => TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT     ,

      TOB_data_FIFO_flags        =>  TOB_data_FIFO_flags ,

      SPY_TOB_mem_wr_addr        =>  SPY_TOB_mem_wr_addr       , -- TOB/XTOB data SPY memory wr addr pointer

      ipbus_out_tob_dpram    =>  ipbus_out_tob_dpram_i    ,    -- o/p signal going to TOB SPY DPRAM

      ipbus_in_tob_dpram     =>  ipbus_in_tob_dpram_i,           -- i/p signal coming from TOB SPY DPRAM

      tob_fsm_monitor        => tob_fsm_monitor

      );


 -- Calorimeter RAW data readout slave registers

 U5_RAW_slave: entity TOB_rdout_lib.slave_RAW_readout

   port map(

      ipb_clk  => ipb_clk,

      ipb_rst  => ipb_rst,

      ipb_in   => ipbw(N_SLV_RAW),

      ipb_out  => ipbr(N_SLV_RAW),

      RAW_WR_ADDR_OFFSET           =>  RAW_WR_ADDR_OFFSET,

      RAW_FIFO_pFULL_THRESH_ASSERT =>  RAW_FIFO_pFULL_THRESH_ASSERT,    -- o/p

      RAW_FIFO_pFULL_THRESH_NEGATE =>  RAW_FIFO_pFULL_THRESH_NEGATE,    -- o/p


      BCN_FIFO_pFULL_THRESH_assert =>    BCN_FIFO_RAW_pFULL_THRESH_assert ,     -- o/p

      BCN_FIFO_pFULL_THRESH_negate =>    BCN_FIFO_RAW_pFULL_THRESH_negate ,     -- o/p

      BCN_FIFO_RAW_rd_data_count   =>    BCN_FIFO_RAW_rd_data_count ,    -- i/p

      Link_output_FIFO_pFULL_THRESH_ASSERT =>  Link_output_FIFO_RAW_pfull_thresh_assert   ,  -- o/p

      Link_output_FIFO_pFULL_THRESH_NEGATE =>  Link_output_FIFO_RAW_pfull_thresh_negate   ,  -- o/p

      Link_output_FIFO_rd_data_count       =>  Link_output_FIFO_RAW_rd_data_count        ,  -- i/p

      RAW_frame_count                      => RAW_frame_count,

      RAW_FIFO_FULL_THRESH_ASSERT   => RAW_FIFO_FULL_THRESH_ASSERT,

      RAW_FIFO_FULL_THRESH_NEGATE   => RAW_FIFO_FULL_THRESH_NEGATE,

      RAW_FIFO_data_count           => RAW_FIFO_data_count,

      raw_busy_thresh_assert        => raw_busy_thresh_assert ,

      raw_busy_thresh_negate        => raw_busy_thresh_negate ,

      RAW_data_FIFO_flags    =>  RAW_data_FIFO_flags,

      SPY_RAW_mem_wr_addr    =>  SPY_RAW_mem_wr_addr   ,  -- RAW calo data SPY memory wr addr pointer

      ipbus_out_raw_dpram    =>  ipbus_out_raw_dpram_i    ,    -- o/p signal going to RAW SPY DPRAM

      ipbus_in_raw_dpram     =>  ipbus_in_raw_dpram_i,           -- i/p signal coming from RAW SPY DPRAM

      link_error_flags       =>  link_error_flags ,      -- 54-b error flags from the Error Flag FIFO to IPBUS register

      raw_fsm_monitor        =>  raw_fsm_monitor


    );


 end Behavioral;

TOB_rdout_ip_pkg
Definition: TOB_rdout_ip_pkg.vhd:34

data_type_pkg
Definition: data_type_pkg.vhd:34

readout_ipb_slave.Behavioral
IPBUS readout slave definitions of registers used in the Top Level Readout Block.
Definition: readout_ipb_slave.vhd:211

readout_ipb_slave
IPBUS readout slave definitions of registers used in the Top Level Readout Block.
Definition: readout_ipb_slave.vhd:57

readout_ipb_slave.RAW_data_FIFO_flags
in RAW_data_FIFO_flags STD_LOGIC_VECTOR( 31 downto  0)
Full and Empty flags for all FIFOs in the RAW Readout Logic.
Definition: readout_ipb_slave.vhd:150

readout_ipb_slave.ipbus_in_tob_dpram
in ipbus_in_tob_dpram ipb_rbus
IPBus access bus signal coming from TOB SPY DPRAM.
Definition: readout_ipb_slave.vhd:156

readout_ipb_slave.TOB_Link_output_FIFO_pFULL_THRESH_NEGATE
out TOB_Link_output_FIFO_pFULL_THRESH_NEGATE STD_LOGIC_VECTOR( 12 downto  0)
Prog Full flag negate threshold for Link Output FIFO of TOBs Readout.
Definition: readout_ipb_slave.vhd:108

readout_ipb_slave.RAW_FIFO_FULL_THRESH_ASSERT
out RAW_FIFO_FULL_THRESH_ASSERT STD_LOGIC_VECTOR( 8 downto  0)
Full flag assert threshold for de-randomisation FIFO of RAW Data Readout.
Definition: readout_ipb_slave.vhd:142

readout_ipb_slave.raw_fsm_monitor
out raw_fsm_monitor std_logic_vector( 31 downto  0)
Monitor RAW Readout state machines.
Definition: readout_ipb_slave.vhd:186

readout_ipb_slave.TOB_WR_ADDR_OFFSET
out TOB_WR_ADDR_OFFSET STD_LOGIC_VECTOR( 8 downto  0)
Write Address Offset for TOB circular DPRAM.
Definition: readout_ipb_slave.vhd:74

readout_ipb_slave.trigger_slice
out trigger_slice STD_LOGIC_VECTOR( 3 downto  0)
Trigger slice number - on L1A.
Definition: readout_ipb_slave.vhd:82

readout_ipb_slave.BCN_FIFO_RAW_rd_data_count
in BCN_FIFO_RAW_rd_data_count STD_LOGIC_VECTOR( 31 downto  0)
BCN & L1A FIFO occupancy for RAW Readout.
Definition: readout_ipb_slave.vhd:134

readout_ipb_slave.ipb_rst
in ipb_rst std_logic
IPBus Reset input.
Definition: readout_ipb_slave.vhd:60

readout_ipb_slave.TOB_SLICES_TO_RD
out TOB_SLICES_TO_RD STD_LOGIC_VECTOR( 2 downto  0)
Number of cosecutive Slices to read from TOBs circular DPRAM.
Definition: readout_ipb_slave.vhd:80

readout_ipb_slave.SPY_RAW_mem_wr_addr
in SPY_RAW_mem_wr_addr STD_LOGIC_VECTOR( 10 downto  0)
Current write address of RAW SPY Memory - used for IPBus access and to calculate occupancy.
Definition: readout_ipb_slave.vhd:160

readout_ipb_slave.busy_tob_duration_counter
in busy_tob_duration_counter STD_LOGIC_VECTOR( 31 downto  0)
Busy counter for TOB BUSY duration.
Definition: readout_ipb_slave.vhd:176

readout_ipb_slave.tob_double_word_counter
in tob_double_word_counter STD_LOGIC_VECTOR( 31 downto  0)
Number of identical TOB double words counter.
Definition: readout_ipb_slave.vhd:184

readout_ipb_slave.TEST_CONTROL_REG
out TEST_CONTROL_REG STD_LOGIC_VECTOR( 31 downto  0)
Test Control Register at Top Level Readout Firmware.
Definition: readout_ipb_slave.vhd:166

readout_ipb_slave.bcn_mismatch_cntr_debug
in bcn_mismatch_cntr_debug std_logic_vector( 31 downto  0)
Mismatch error count on BCN.
Definition: readout_ipb_slave.vhd:207

readout_ipb_slave.tob_busy_thresh_assert
out tob_busy_thresh_assert STD_LOGIC_VECTOR( 8 downto  0)
sorted TOB BUSY flag threshold assert
Definition: readout_ipb_slave.vhd:90

readout_ipb_slave.BCN_FIFO_RAW_pFULL_THRESH_assert
out BCN_FIFO_RAW_pFULL_THRESH_assert STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag assert threshold for TTC FIFO.
Definition: readout_ipb_slave.vhd:130

readout_ipb_slave.RAW_FIFO_data_count
in RAW_FIFO_data_count STD_LOGIC_VECTOR( 31 downto  0)
Occupancy level ofde-randomisation FIFO of RAW Data Readout.
Definition: readout_ipb_slave.vhd:146

readout_ipb_slave.TOB_data_FIFO_flags
in TOB_data_FIFO_flags STD_LOGIC_VECTOR( 31 downto  0)
Full and Empty flags for all FIFOs in the TOBs Readout Logic.
Definition: readout_ipb_slave.vhd:112

readout_ipb_slave.raw_busy_thresh_assert
out raw_busy_thresh_assert STD_LOGIC_VECTOR( 8 downto  0)
raw BUSY flag threshold assert
Definition: readout_ipb_slave.vhd:120

readout_ipb_slave.busy_raw_counter
in busy_raw_counter STD_LOGIC_VECTOR( 31 downto  0)
Busy counter for RAW data buffers.
Definition: readout_ipb_slave.vhd:170

readout_ipb_slave.XTOB_TAU_WR_ADDR_OFFSET
out XTOB_TAU_WR_ADDR_OFFSET STD_LOGIC_VECTOR( 8 downto  0)
Write Address Offset for XTOB tau circular DPRAM.
Definition: readout_ipb_slave.vhd:78

readout_ipb_slave.BCN_FIFO_RAW_pFULL_THRESH_negate
out BCN_FIFO_RAW_pFULL_THRESH_negate STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag negate threshold for TTC FIFO.
Definition: readout_ipb_slave.vhd:132

readout_ipb_slave.l1id_parity_err_cntr_debug
in l1id_parity_err_cntr_debug std_logic_vector( 31 downto  0)
Parity error count on L1A.
Definition: readout_ipb_slave.vhd:200

readout_ipb_slave.tob_fsm_monitor
out tob_fsm_monitor std_logic_vector( 39 downto  0)
Monitor TOB Readout state machines.
Definition: readout_ipb_slave.vhd:188

readout_ipb_slave.XTOB_TAU_FIFO_pFULL_THRESH_ASSERT
out XTOB_TAU_FIFO_pFULL_THRESH_ASSERT STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag assert threshold for de-randomisation FIFO of XTOBs tau Readout.
Definition: readout_ipb_slave.vhd:100

readout_ipb_slave.RDOUT_PULSE_REG
out RDOUT_PULSE_REG STD_LOGIC_VECTOR( 31 downto  0)
Control Pulse Register for RAW Readout, all values are set to ZERO following a write to this register...
Definition: readout_ipb_slave.vhd:158

readout_ipb_slave.XTOB_TAU_FIFO_DATA_COUNT
in XTOB_TAU_FIFO_DATA_COUNT STD_LOGIC_VECTOR( 31 downto  0)
Occupancy level of de-randomisation FIFO of XTOBs tau Readout.
Definition: readout_ipb_slave.vhd:104

readout_ipb_slave.IPb_out
out IPb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: readout_ipb_slave.vhd:66

readout_ipb_slave.RAW_FIFO_pFULL_THRESH_ASSERT
out RAW_FIFO_pFULL_THRESH_ASSERT STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag assert threshold for de-randomisation FIFO of RAW Data Readout.
Definition: readout_ipb_slave.vhd:116

readout_ipb_slave.BCN_FIFO_TOB_pFULL_THRESH_negate
out BCN_FIFO_TOB_pFULL_THRESH_negate STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag negate threshold for TTC FIFO.
Definition: readout_ipb_slave.vhd:126

readout_ipb_slave.BCN_FIFO_TOB_pFULL_THRESH_assert
out BCN_FIFO_TOB_pFULL_THRESH_assert STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag assert threshold for TTC FIFO.
Definition: readout_ipb_slave.vhd:124

readout_ipb_slave.RAW_frame_count
in RAW_frame_count STD_LOGIC_VECTOR( 31 downto  0)
Number of complete RAW Frames in Link Output FIFO to be transmitted to cFPGA.
Definition: readout_ipb_slave.vhd:148

readout_ipb_slave.ttc_err_history_debug
in ttc_err_history_debug std_logic_vector( 31 downto  0)
History of last 8 TTC errors.
Definition: readout_ipb_slave.vhd:190

readout_ipb_slave.SPY_TOB_mem_wr_addr
in SPY_TOB_mem_wr_addr STD_LOGIC_VECTOR( 10 downto  0)
Current write address of TOBs SPY Memory - used for IPBus access and to calculate occupancy.
Definition: readout_ipb_slave.vhd:152

readout_ipb_slave.RAW_FIFO_pFULL_THRESH_NEGATE
out RAW_FIFO_pFULL_THRESH_NEGATE STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag negate threshold for de-randomisation FIFO of RAW Data Readout.
Definition: readout_ipb_slave.vhd:118

readout_ipb_slave.L1A_ID
in L1A_ID STD_LOGIC_VECTOR( 31 downto  0)
8b Extended L1A ID + 24b L1A ID of L1A counter
Definition: readout_ipb_slave.vhd:70

readout_ipb_slave.XTOB_EG_WR_ADDR_OFFSET
out XTOB_EG_WR_ADDR_OFFSET STD_LOGIC_VECTOR( 8 downto  0)
Write Address Offset for XTOB e/g circular DPRAM.
Definition: readout_ipb_slave.vhd:76

readout_ipb_slave.raw_busy_thresh_negate
out raw_busy_thresh_negate STD_LOGIC_VECTOR( 8 downto  0)
raw BUSY flag threshold de-assert
Definition: readout_ipb_slave.vhd:122

readout_ipb_slave.l1a_id_err_debug
in l1a_id_err_debug std_logic_vector( 31 downto  0)
Shows last corrupt L1A ID.
Definition: readout_ipb_slave.vhd:194

readout_ipb_slave.bcn_err_expected_debug
in bcn_err_expected_debug std_logic_vector( 31 downto  0)
Error, bad BCN and expected BCN on BCN error.
Definition: readout_ipb_slave.vhd:198

readout_ipb_slave.IPb_in
in IPb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: readout_ipb_slave.vhd:64

readout_ipb_slave.link_error_flags
in link_error_flags STD_LOGIC_VECTOR( 53 downto  0)
54-b error flags from the Error Flag FIFO to IPBUS register
Definition: readout_ipb_slave.vhd:168

readout_ipb_slave.ipb_clk
in ipb_clk std_logic
IPBus Clock input.
Definition: readout_ipb_slave.vhd:62

readout_ipb_slave.XTOB_EG_FIFO_DATA_COUNT
in XTOB_EG_FIFO_DATA_COUNT STD_LOGIC_VECTOR( 31 downto  0)
Occupancy level of de-randomisation FIFO of XTOBs e/g Readout.
Definition: readout_ipb_slave.vhd:98

readout_ipb_slave.XTOB_TAU_FIFO_pFULL_THRESH_NEGATE
out XTOB_TAU_FIFO_pFULL_THRESH_NEGATE STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag negate threshold for de-randomisation FIFO of XTOBs tau Readout.
Definition: readout_ipb_slave.vhd:102

readout_ipb_slave.l1a_id_good_debug
in l1a_id_good_debug std_logic_vector( 31 downto  0)
Shows last good L1A ID.
Definition: readout_ipb_slave.vhd:192

readout_ipb_slave.TOB_FIFO_DATA_COUNT
in TOB_FIFO_DATA_COUNT STD_LOGIC_VECTOR( 31 downto  0)
Occupancy level of de-randomisation FIFO of TOBs Readout.
Definition: readout_ipb_slave.vhd:88

readout_ipb_slave.RAW_FIFO_FULL_THRESH_NEGATE
out RAW_FIFO_FULL_THRESH_NEGATE STD_LOGIC_VECTOR( 8 downto  0)
Full flag negate threshold for de-randomisation FIFO of RAW Data Readout.
Definition: readout_ipb_slave.vhd:144

readout_ipb_slave.busy_tob_counter
in busy_tob_counter STD_LOGIC_VECTOR( 31 downto  0)
Busy counter for TOB data buffers.
Definition: readout_ipb_slave.vhd:172

readout_ipb_slave.real_time_40m_counter
in real_time_40m_counter STD_LOGIC_VECTOR( 31 downto  0)
Real time 40MHz counter, counting number of 40MHz ticks.
Definition: readout_ipb_slave.vhd:182

readout_ipb_slave.ipbus_out_tob_dpram
out ipbus_out_tob_dpram ipb_wbus
IPBus access bus signal going to TOB SPY DPRAM.
Definition: readout_ipb_slave.vhd:154

readout_ipb_slave.busy_raw_duration_counter
in busy_raw_duration_counter STD_LOGIC_VECTOR( 31 downto  0)
Busy counter for RAW BUSY Duration.
Definition: readout_ipb_slave.vhd:174

readout_ipb_slave.L1A_ID_Event
in L1A_ID_Event STD_LOGIC_VECTOR( 31 downto  0)
8b Ext L1A ID from TTC input + 24b L1A ID of counter from TTC FIFO - inserted in the event header
Definition: readout_ipb_slave.vhd:68

readout_ipb_slave.Link_output_FIFO_RAW_rd_data_count
in Link_output_FIFO_RAW_rd_data_count STD_LOGIC_VECTOR( 31 downto  0)
Occupancy level of Link Output FIFO of RAW Data Readout.
Definition: readout_ipb_slave.vhd:136

readout_ipb_slave.BCN_FIFO_TOB_rd_data_count
in BCN_FIFO_TOB_rd_data_count STD_LOGIC_VECTOR( 31 downto  0)
BCN & L1A FIFO occupancy for TOB Readout.
Definition: readout_ipb_slave.vhd:128

readout_ipb_slave.bcn_parity_err_cntr_debug
in bcn_parity_err_cntr_debug std_logic_vector( 31 downto  0)
Parity error count on BCN.
Definition: readout_ipb_slave.vhd:204

readout_ipb_slave.Link_output_FIFO_RAW_pfull_thresh_assert
out Link_output_FIFO_RAW_pfull_thresh_assert STD_LOGIC_VECTOR( 12 downto  0)
Prog Full flag assert threshold for Link Output FIFO of RAW Data Readout.
Definition: readout_ipb_slave.vhd:138

readout_ipb_slave.RAW_WR_ADDR_OFFSET
out RAW_WR_ADDR_OFFSET STD_LOGIC_VECTOR( 9 downto  0)
Write Address Offset for RAW circular DPRAM.
Definition: readout_ipb_slave.vhd:114

readout_ipb_slave.tob_busy_thresh_negate
out tob_busy_thresh_negate STD_LOGIC_VECTOR( 8 downto  0)
sorted TOB BUSY flag threshold de-assert
Definition: readout_ipb_slave.vhd:92

readout_ipb_slave.l1a_id_expected_debug
in l1a_id_expected_debug std_logic_vector( 31 downto  0)
Shows last expected L1A ID on error.
Definition: readout_ipb_slave.vhd:196

readout_ipb_slave.TOB_FIFO_pFULL_THRESH_NEGATE
out TOB_FIFO_pFULL_THRESH_NEGATE STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag negate threshold for de-randomisation FIFO of TOBs Readout.
Definition: readout_ipb_slave.vhd:86

readout_ipb_slave.Link_output_FIFO_RAW_pfull_thresh_negate
out Link_output_FIFO_RAW_pfull_thresh_negate STD_LOGIC_VECTOR( 12 downto  0)
Prog Full flag negate threshold for Link Output FIFO of RAW Data Readout.
Definition: readout_ipb_slave.vhd:140

readout_ipb_slave.TOB_FIFO_pFULL_THRESH_ASSERT
out TOB_FIFO_pFULL_THRESH_ASSERT STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag assert threshold for de-randomisation FIFO of TOBs Readout.
Definition: readout_ipb_slave.vhd:84

readout_ipb_slave.XTOB_EG_FIFO_pFULL_THRESH_ASSERT
out XTOB_EG_FIFO_pFULL_THRESH_ASSERT STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag assert threshold for de-randomisation FIFO of XTOBs e/g Readout.
Definition: readout_ipb_slave.vhd:94

readout_ipb_slave.l1id_mismatch_cntr_debug
in l1id_mismatch_cntr_debug std_logic_vector( 31 downto  0)
Mismatch error count on L1A.
Definition: readout_ipb_slave.vhd:202

readout_ipb_slave.TOB_Link_output_FIFO_pFULL_THRESH_ASSERT
out TOB_Link_output_FIFO_pFULL_THRESH_ASSERT STD_LOGIC_VECTOR( 12 downto  0)
Prog Full flag assert threshold for Link Output FIFO of TOBs Readout.
Definition: readout_ipb_slave.vhd:106

readout_ipb_slave.ipbus_out_raw_dpram
out ipbus_out_raw_dpram ipb_wbus
IPBus access bus signal going to RAW SPY DPRAM.
Definition: readout_ipb_slave.vhd:162

readout_ipb_slave.TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT
in TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT STD_LOGIC_VECTOR( 31 downto  0)
Occupancy level of Link Output FIFO of TOBs Readout.
Definition: readout_ipb_slave.vhd:110

readout_ipb_slave.ipbus_in_raw_dpram
in ipbus_in_raw_dpram ipb_rbus
IPBus access bus signal coming from RAW SPY DPRAM.
Definition: readout_ipb_slave.vhd:164

readout_ipb_slave.BCN_in
in BCN_in STD_LOGIC_VECTOR( 11 downto  0)
Bunch Crossing Number.
Definition: readout_ipb_slave.vhd:72

readout_ipb_slave.L1A_debug_counter
in L1A_debug_counter STD_LOGIC_VECTOR( 31 downto  0)
L1A_debug_counter.
Definition: readout_ipb_slave.vhd:180

readout_ipb_slave.ECR_debug_counter
in ECR_debug_counter STD_LOGIC_VECTOR( 31 downto  0)
ECR_debug_counter.
Definition: readout_ipb_slave.vhd:178

readout_ipb_slave.XTOB_EG_FIFO_pFULL_THRESH_NEGATE
out XTOB_EG_FIFO_pFULL_THRESH_NEGATE STD_LOGIC_VECTOR( 8 downto  0)
Prog Full flag negate threshold for de-randomisation FIFO of XTOBs e/g Readout.
Definition: readout_ipb_slave.vhd:96

slave_RAW_readout
RAW calorimeter data readout slave registers.
Definition: slave_RAW_readout.vhd:44

slave_RAW_readout.BCN_FIFO_RAW_rd_data_count
in BCN_FIFO_RAW_rd_data_count STD_LOGIC_VECTOR( 31 downto  0)
BCN & L1A FIFO occupancy for RAW Readout.
Definition: slave_RAW_readout.vhd:65

slave_RAW_readout.RAW_FIFO_data_count
in RAW_FIFO_data_count std_logic_vector( 31 downto  0)
Derandomisation FIFO FIFO occupancy data count.
Definition: slave_RAW_readout.vhd:81

slave_RAW_readout.Link_output_FIFO_pFULL_THRESH_ASSERT
out Link_output_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 12 downto  0)
Link output FIFO (before MGT) partial full flag assert threshold.
Definition: slave_RAW_readout.vhd:68

slave_RAW_readout.ipb_rst
in ipb_rst std_logic
IPBus Reset input.
Definition: slave_RAW_readout.vhd:47

slave_RAW_readout.RAW_WR_ADDR_OFFSET
out RAW_WR_ADDR_OFFSET std_logic_vector( 9 downto  0)
The write address offset pre load for RAW data Circular DRPAM.
Definition: slave_RAW_readout.vhd:90

slave_RAW_readout.raw_busy_thresh_assert
out raw_busy_thresh_assert STD_LOGIC_VECTOR( 8 downto  0)
raw BUSY flag threshold assert
Definition: slave_RAW_readout.vhd:83

slave_RAW_readout.Link_output_FIFO_pFULL_THRESH_NEGATE
out Link_output_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 12 downto  0)
Link output FIFO (before MGT) partial full flag negate threshold.
Definition: slave_RAW_readout.vhd:70

slave_RAW_readout.Link_output_FIFO_rd_data_count
in Link_output_FIFO_rd_data_count std_logic_vector( 31 downto  0)
Link output FIFO (before MGT) occupancy data count.
Definition: slave_RAW_readout.vhd:72

slave_RAW_readout.raw_busy_thresh_negate
out raw_busy_thresh_negate STD_LOGIC_VECTOR( 8 downto  0)
raw BUSY flag threshold de-assert
Definition: slave_RAW_readout.vhd:85

slave_RAW_readout.RAW_data_FIFO_flags
in RAW_data_FIFO_flags std_logic_vector( 31 downto  0)
Read only register containing all Empty pFull and Full of RAW data block.
Definition: slave_RAW_readout.vhd:88

slave_RAW_readout.RAW_frame_count
in RAW_frame_count std_logic_vector( 31 downto  0)
numer of frames in the link output FIFO to be transmitted to MGT & Control FPGA
Definition: slave_RAW_readout.vhd:74

slave_RAW_readout.link_error_flags
in link_error_flags STD_LOGIC_VECTOR( 53 downto  0)
54-b error flags from the Error Flag FIFO to IPBUS register
Definition: slave_RAW_readout.vhd:98

slave_RAW_readout.ipb_clk
in ipb_clk std_logic
IPBus Clock input.
Definition: slave_RAW_readout.vhd:49

slave_RAW_readout.SPY_RAW_mem_wr_addr
in SPY_RAW_mem_wr_addr std_logic_vector( 10 downto  0)
RAW SPY Memory write address (read only register)
Definition: slave_RAW_readout.vhd:92

slave_RAW_readout.RAW_FIFO_FULL_THRESH_NEGATE
out RAW_FIFO_FULL_THRESH_NEGATE std_logic_vector( 8 downto  0)
36b derandomisation FIFO full flag negate threshold
Definition: slave_RAW_readout.vhd:79

slave_RAW_readout.RAW_FIFO_pFULL_THRESH_ASSERT
out RAW_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 8 downto  0)
Derandomisation FIFO partial full flag assert threshold.
Definition: slave_RAW_readout.vhd:56

slave_RAW_readout.BCN_FIFO_pFULL_THRESH_negate
out BCN_FIFO_pFULL_THRESH_negate std_logic_vector( 8 downto  0)
BCN FIFO partial full flag negate threshold.
Definition: slave_RAW_readout.vhd:63

slave_RAW_readout.BCN_FIFO_pFULL_THRESH_assert
out BCN_FIFO_pFULL_THRESH_assert std_logic_vector( 8 downto  0)
BCN FIFO partial full flag assert threshold.
Definition: slave_RAW_readout.vhd:61

slave_RAW_readout.ipbus_out_raw_dpram
out ipbus_out_raw_dpram ipb_wbus
IPBus signal going to RAW SPY DPRAM.
Definition: slave_RAW_readout.vhd:94

slave_RAW_readout.RAW_FIFO_FULL_THRESH_ASSERT
out RAW_FIFO_FULL_THRESH_ASSERT std_logic_vector( 8 downto  0)
Derandomisation FIFO full flag assert threshold.
Definition: slave_RAW_readout.vhd:77

slave_RAW_readout.RAW_FIFO_pFULL_THRESH_NEGATE
out RAW_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 8 downto  0)
36b derandomisation FIFO partial full flag negate threshold
Definition: slave_RAW_readout.vhd:58

slave_RAW_readout.ipbus_in_raw_dpram
in ipbus_in_raw_dpram ipb_rbus
IPBus signal coming from RAW SPY DPRAM.
Definition: slave_RAW_readout.vhd:96

slave_RAW_readout.raw_fsm_monitor
in raw_fsm_monitor std_logic_vector( 31 downto  0)
Monitor RAW Readout state machines.
Definition: slave_RAW_readout.vhd:101

slave_TOB_readout
TOB/XTOB data readout slave registers.
Definition: slave_TOB_readout.vhd:54

slave_TOB_readout.ipbus_in_tob_dpram
in ipbus_in_tob_dpram ipb_rbus
IPBus signal coming from TOB/XTOB SPY DPRAM.
Definition: slave_TOB_readout.vhd:121

slave_TOB_readout.TOB_WR_ADDR_OFFSET
out TOB_WR_ADDR_OFFSET std_logic_vector( 8 downto  0)
The write address offset pre load for TOB Circular DRPAM.
Definition: slave_TOB_readout.vhd:71

slave_TOB_readout.TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT
in TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT std_logic_vector( 31 downto  0)
Link output FIFO (before MGT) occupancy data count.
Definition: slave_TOB_readout.vhd:113

slave_TOB_readout.trigger_slice
out trigger_slice STD_LOGIC_VECTOR( 3 downto  0)
Trigger slice number - on L1A.
Definition: slave_TOB_readout.vhd:79

slave_TOB_readout.TOB_SLICES_TO_RD
out TOB_SLICES_TO_RD std_logic_vector( 2 downto  0)
number of DRP locations (Slices) to read 1 to 5
Definition: slave_TOB_readout.vhd:77

slave_TOB_readout.ipb_rst
in ipb_rst std_logic
IPBus Reset input.
Definition: slave_TOB_readout.vhd:57

slave_TOB_readout.TOB_Link_output_FIFO_pFULL_THRESH_ASSERT
out TOB_Link_output_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 12 downto  0)
Link output FIFO (before MGT) partial full flag assert threshold.
Definition: slave_TOB_readout.vhd:109

slave_TOB_readout.tob_busy_thresh_assert
out tob_busy_thresh_assert STD_LOGIC_VECTOR( 8 downto  0)
sorted TOB BUSY flag threshold assert
Definition: slave_TOB_readout.vhd:93

slave_TOB_readout.XTOB_TAU_WR_ADDR_OFFSET
out XTOB_TAU_WR_ADDR_OFFSET std_logic_vector( 8 downto  0)
The write address offset pre load for XTOB tau Circular DRPAM.
Definition: slave_TOB_readout.vhd:75

slave_TOB_readout.XTOB_EG_FIFO_DATA_COUNT
in XTOB_EG_FIFO_DATA_COUNT std_logic_vector( 31 downto  0)
XTOB e/g Derandomisation FIFO FIFO occupancy data count.
Definition: slave_TOB_readout.vhd:101

slave_TOB_readout.TOB_FIFO_pFULL_THRESH_NEGATE
out TOB_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 8 downto  0)
TOB Derandomisation FIFO partial full flag negate threshold.
Definition: slave_TOB_readout.vhd:89

slave_TOB_readout.XTOB_EG_FIFO_pFULL_THRESH_NEGATE
out XTOB_EG_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 8 downto  0)
XTOB e/g Derandomisation FIFO partial full flag negate threshold.
Definition: slave_TOB_readout.vhd:99

slave_TOB_readout.XTOB_EG_FIFO_pFULL_THRESH_ASSERT
out XTOB_EG_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 8 downto  0)
XTOB e/g Derandomisation FIFO partial full flag assert threshold.
Definition: slave_TOB_readout.vhd:97

slave_TOB_readout.XTOB_TAU_FIFO_pFULL_THRESH_ASSERT
out XTOB_TAU_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 8 downto  0)
XTOB tau Derandomisation FIFO partial full flag assert threshold.
Definition: slave_TOB_readout.vhd:103

slave_TOB_readout.TOB_Link_output_FIFO_pFULL_THRESH_NEGATE
out TOB_Link_output_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 12 downto  0)
Link output FIFO (before MGT) partial full flag negate threshold.
Definition: slave_TOB_readout.vhd:111

slave_TOB_readout.L1A_ID
in L1A_ID std_logic_vector( 31 downto  0)
8b Extended L1A ID + 24b L1A ID of counter
Definition: slave_TOB_readout.vhd:67

slave_TOB_readout.XTOB_TAU_FIFO_pFULL_THRESH_NEGATE
out XTOB_TAU_FIFO_pFULL_THRESH_NEGATE std_logic_vector( 8 downto  0)
XTOB tau Derandomisation FIFO partial full flag negate threshold.
Definition: slave_TOB_readout.vhd:105

slave_TOB_readout.TOB_FIFO_DATA_COUNT
in TOB_FIFO_DATA_COUNT std_logic_vector( 31 downto  0)
TOB Derandomisation FIFO FIFO occupancy data count.
Definition: slave_TOB_readout.vhd:91

slave_TOB_readout.ipb_clk
in ipb_clk std_logic
IPBus Clock input.
Definition: slave_TOB_readout.vhd:59

slave_TOB_readout.XTOB_TAU_FIFO_DATA_COUNT
in XTOB_TAU_FIFO_DATA_COUNT std_logic_vector( 31 downto  0)
XTOB tau Derandomisation FIFO FIFO occupancy data count.
Definition: slave_TOB_readout.vhd:107

slave_TOB_readout.SPY_TOB_mem_wr_addr
in SPY_TOB_mem_wr_addr std_logic_vector( 10 downto  0)
TOB/XTOB SPY Memory write address (read only register)
Definition: slave_TOB_readout.vhd:117

slave_TOB_readout.ipbus_out_tob_dpram
out ipbus_out_tob_dpram ipb_wbus
IPBus signal going to TOB/XTOB SPY DPRAM.
Definition: slave_TOB_readout.vhd:119

slave_TOB_readout.TOB_FIFO_pFULL_THRESH_ASSERT
out TOB_FIFO_pFULL_THRESH_ASSERT std_logic_vector( 8 downto  0)
TOB Derandomisation FIFO partial full flag assert threshold.
Definition: slave_TOB_readout.vhd:87

slave_TOB_readout.tob_fsm_monitor
in tob_fsm_monitor std_logic_vector( 39 downto  0)
Monitor TOB Readout state machines.
Definition: slave_TOB_readout.vhd:124

slave_TOB_readout.BCN_FIFO_TOB_rd_data_count
in BCN_FIFO_TOB_rd_data_count STD_LOGIC_VECTOR( 31 downto  0)
BCN & L1A FIFO occupancy for TOB Readout.
Definition: slave_TOB_readout.vhd:85

slave_TOB_readout.tob_busy_thresh_negate
out tob_busy_thresh_negate STD_LOGIC_VECTOR( 8 downto  0)
sorted TOB BUSY flag threshold de-assert
Definition: slave_TOB_readout.vhd:95

slave_TOB_readout.TOB_data_FIFO_flags
in TOB_data_FIFO_flags std_logic_vector( 31 downto  0)
Read only register containing all Empty pFull and Full of TOB/XTOB data block.
Definition: slave_TOB_readout.vhd:115

slave_TOB_readout.XTOB_EG_WR_ADDR_OFFSET
out XTOB_EG_WR_ADDR_OFFSET std_logic_vector( 8 downto  0)
The write address offset pre load for XTOB e/g Circular DRPAM.
Definition: slave_TOB_readout.vhd:73

slave_TOB_readout.L1A_ID_Event
in L1A_ID_Event std_logic_vector( 31 downto  0)
8b Ext L1A ID from TTC input + 24b L1A ID of counter from TTC FIFO - inserted in the event header
Definition: slave_TOB_readout.vhd:65

slave_TOB_readout.BCN_FIFO_pFULL_THRESH_negate
out BCN_FIFO_pFULL_THRESH_negate std_logic_vector( 8 downto  0)
BCN FIFO partial full flag negate threshold.
Definition: slave_TOB_readout.vhd:83

slave_TOB_readout.BCN_FIFO_pFULL_THRESH_assert
out BCN_FIFO_pFULL_THRESH_assert std_logic_vector( 8 downto  0)
BCN FIFO partial full flag assert threshold.
Definition: slave_TOB_readout.vhd:81

slave_TOB_readout.BCN_in
in BCN_in std_logic_vector( 11 downto  0)
Bunch Crossing number input.
Definition: slave_TOB_readout.vhd:69