Behavioral Architecture Reference

IPBUS readout slave definitions of registers used in the Top Level Readout Block. More...

Processes
U4_rst_pulse_reg	( ipb_clk )

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
ipbr_d	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
RDOUT_PULSE_REG_i	STD_LOGIC_VECTOR ( 31 downto 0 )
rst_pulse_reg_i	STD_LOGIC := ' 0 '
rst_pulse_reg_ii	STD_LOGIC
IPbw_in_i	ipb_wbus
IPbr_out_i	ipb_rbus
TEST_CONTROL_REG_i	STD_LOGIC_VECTOR ( 31 downto 0 )
rst_ECR_dbg_cntr_i	STD_LOGIC := ' 0 '
rst_L1A_dbg_cntr_i	STD_LOGIC := ' 0 '
ipbus_out_raw_dpram_i	ipb_wbus
ipbus_in_raw_dpram_i	ipb_rbus
ipbus_out_tob_dpram_i	ipb_wbus
ipbus_in_tob_dpram_i	ipb_rbus

Instantiations
u1_rdout_fabric	ipbus_fabric_sel
u2_test_cntl_reg	ipbus_ctrlreg_v
u3_pulsed_register	ipbus_ctrlreg_v
u3_top_level_counters	ipbus_ctrlreg_v
u3_ttc_parity_l1a_bcn	ipbus_ctrlreg_v
u4_tob_slave	slave_TOB_readout <Entity slave_TOB_readout>
u5_raw_slave	slave_RAW_readout <Entity slave_RAW_readout>

Detailed Description

IPBUS readout slave definitions of registers used in the Top Level Readout Block.

This is the IPBUS readout slave definitions of registers used in the Top Level Readout Block. There are 3 section:

1. Top Level IPBUS Fabric and Registers.
2. RAW Calorimeter Readout Registers.
3. XTOB/TOB Readout Registers.

There are two registers at this level, therefore there is a need for a IPBUS Fabric Module.

The IPBus bus fabric, which also has address select logic and data multiplexers. This version selects the addressed slave depending on the state of incoming control lines.

The control register is a 32b register, which is read/written through the IPBus.

• bit 0 : 1 = all fibre readout, 0 = error fibre readout

The Pulse Registe is 32b register, which is read/written through the IPBus.

• This is a pulse register and automatically resets to ZERO after one clock cycle.
• bit 0 = Not Used
• bit 1 = Reset 24-bit L1A_ID counter
• bit 2 = Reset FIFOs and FSMs in RAW Readout module
• bit 3 = Reset FIFOs and FSMs in TOB Readout module
• bit 4 = Not Used
• bit 5 = Reset SPY RAM Write address to Zero for both RAW and TOB Readout
• bit 6 = Reset BUSY counter for RAW and TOB data
• bit 7 = Reset ECR Debug Counter
• bit 8 = Reset L1A Debug Counter
• bit 9 = Latch BUSY Counters for readout by TDAQ software

Top Level Counters, which are read through the IPBus.

• Addr 0 = BUSY RAW counter - Number of RAW Readout BUSY assertions
• Addr 1 = BUSY TOB counter - Number of TOB Readout BUSY assertions
• Addr 2 = BUSY RAW Duration counter - Number of 40M clocks RAW Readout BUSY is asserted
• Addr 3 = BUSY TOB Duration counter - Number of 40M clocks TOB Readout BUSY is asserted
• Addr 4 = ECR Debug Counter
• Addr 5 = L1A Debug Counter
• Addr 6 = Real Time 40M Counter - Number of 40M clocks
• Addr 7 = TOB Double Word Counter - Number of identical TOB double words

Author

Saeed Taghavi

Definition at line 211 of file readout_ipb_slave.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/readout_ipb_slave.vhd