readout_ipb_slave Entity Reference

IPBUS readout slave definitions of registers used in the Top Level Readout Block. More...

Inheritance diagram for readout_ipb_slave:

Entities
Behavioral	architecture
	IPBUS readout slave definitions of registers used in the Top Level Readout Block. More...

Libraries
IEEE
ipbus_lib
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
ipbus
data_type_pkg	Package <data_type_pkg>
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
ipbus_decode_efex_readout

Ports
ipb_rst	in	std_logic
		IPBus Reset input.
ipb_clk	in	std_logic
		IPBus Clock input.
IPb_in	in	ipb_wbus
		IPBus input bus going from master to slaves.
IPb_out	out	ipb_rbus
		IPBus output bus going from slaves to master.
L1A_ID_Event	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		8b Ext L1A ID from TTC input + 24b L1A ID of counter from TTC FIFO - inserted in the event header
L1A_ID	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		8b Extended L1A ID + 24b L1A ID of L1A counter
BCN_in	in	STD_LOGIC_VECTOR ( 11 downto 0 )
		Bunch Crossing Number.
TOB_WR_ADDR_OFFSET	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Write Address Offset for TOB circular DPRAM.
XTOB_EG_WR_ADDR_OFFSET	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Write Address Offset for XTOB e/g circular DPRAM.
XTOB_TAU_WR_ADDR_OFFSET	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Write Address Offset for XTOB tau circular DPRAM.
TOB_SLICES_TO_RD	out	STD_LOGIC_VECTOR ( 2 downto 0 )
		Number of cosecutive Slices to read from TOBs circular DPRAM.
trigger_slice	out	STD_LOGIC_VECTOR ( 3 downto 0 )
		Trigger slice number - on L1A.
TOB_FIFO_pFULL_THRESH_ASSERT	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag assert threshold for de-randomisation FIFO of TOBs Readout.
TOB_FIFO_pFULL_THRESH_NEGATE	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag negate threshold for de-randomisation FIFO of TOBs Readout.
TOB_FIFO_DATA_COUNT	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Occupancy level of de-randomisation FIFO of TOBs Readout.
tob_busy_thresh_assert	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		sorted TOB BUSY flag threshold assert
tob_busy_thresh_negate	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		sorted TOB BUSY flag threshold de-assert
XTOB_EG_FIFO_pFULL_THRESH_ASSERT	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag assert threshold for de-randomisation FIFO of XTOBs e/g Readout.
XTOB_EG_FIFO_pFULL_THRESH_NEGATE	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag negate threshold for de-randomisation FIFO of XTOBs e/g Readout.
XTOB_EG_FIFO_DATA_COUNT	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Occupancy level of de-randomisation FIFO of XTOBs e/g Readout.
XTOB_TAU_FIFO_pFULL_THRESH_ASSERT	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag assert threshold for de-randomisation FIFO of XTOBs tau Readout.
XTOB_TAU_FIFO_pFULL_THRESH_NEGATE	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag negate threshold for de-randomisation FIFO of XTOBs tau Readout.
XTOB_TAU_FIFO_DATA_COUNT	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Occupancy level of de-randomisation FIFO of XTOBs tau Readout.
TOB_Link_output_FIFO_pFULL_THRESH_ASSERT	out	STD_LOGIC_VECTOR ( 12 downto 0 )
		Prog Full flag assert threshold for Link Output FIFO of TOBs Readout.
TOB_Link_output_FIFO_pFULL_THRESH_NEGATE	out	STD_LOGIC_VECTOR ( 12 downto 0 )
		Prog Full flag negate threshold for Link Output FIFO of TOBs Readout.
TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Occupancy level of Link Output FIFO of TOBs Readout.
TOB_data_FIFO_flags	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Full and Empty flags for all FIFOs in the TOBs Readout Logic.
RAW_WR_ADDR_OFFSET	out	STD_LOGIC_VECTOR ( 9 downto 0 )
		Write Address Offset for RAW circular DPRAM.
RAW_FIFO_pFULL_THRESH_ASSERT	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag assert threshold for de-randomisation FIFO of RAW Data Readout.
RAW_FIFO_pFULL_THRESH_NEGATE	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag negate threshold for de-randomisation FIFO of RAW Data Readout.
raw_busy_thresh_assert	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		raw BUSY flag threshold assert
raw_busy_thresh_negate	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		raw BUSY flag threshold de-assert
BCN_FIFO_TOB_pFULL_THRESH_assert	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag assert threshold for TTC FIFO.
BCN_FIFO_TOB_pFULL_THRESH_negate	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag negate threshold for TTC FIFO.
BCN_FIFO_TOB_rd_data_count	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		BCN & L1A FIFO occupancy for TOB Readout.
BCN_FIFO_RAW_pFULL_THRESH_assert	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag assert threshold for TTC FIFO.
BCN_FIFO_RAW_pFULL_THRESH_negate	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Prog Full flag negate threshold for TTC FIFO.
BCN_FIFO_RAW_rd_data_count	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		BCN & L1A FIFO occupancy for RAW Readout.
Link_output_FIFO_RAW_rd_data_count	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Occupancy level of Link Output FIFO of RAW Data Readout.
Link_output_FIFO_RAW_pfull_thresh_assert	out	STD_LOGIC_VECTOR ( 12 downto 0 )
		Prog Full flag assert threshold for Link Output FIFO of RAW Data Readout.
Link_output_FIFO_RAW_pfull_thresh_negate	out	STD_LOGIC_VECTOR ( 12 downto 0 )
		Prog Full flag negate threshold for Link Output FIFO of RAW Data Readout.
RAW_FIFO_FULL_THRESH_ASSERT	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Full flag assert threshold for de-randomisation FIFO of RAW Data Readout.
RAW_FIFO_FULL_THRESH_NEGATE	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Full flag negate threshold for de-randomisation FIFO of RAW Data Readout.
RAW_FIFO_data_count	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Occupancy level ofde-randomisation FIFO of RAW Data Readout.
RAW_frame_count	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Number of complete RAW Frames in Link Output FIFO to be transmitted to cFPGA.
RAW_data_FIFO_flags	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Full and Empty flags for all FIFOs in the RAW Readout Logic.
SPY_TOB_mem_wr_addr	in	STD_LOGIC_VECTOR ( 10 downto 0 )
		Current write address of TOBs SPY Memory - used for IPBus access and to calculate occupancy.
ipbus_out_tob_dpram	out	ipb_wbus
		IPBus access bus signal going to TOB SPY DPRAM.
ipbus_in_tob_dpram	in	ipb_rbus
		IPBus access bus signal coming from TOB SPY DPRAM.
RDOUT_PULSE_REG	out	STD_LOGIC_VECTOR ( 31 downto 0 )
		Control Pulse Register for RAW Readout, all values are set to ZERO following a write to this register.
SPY_RAW_mem_wr_addr	in	STD_LOGIC_VECTOR ( 10 downto 0 )
		Current write address of RAW SPY Memory - used for IPBus access and to calculate occupancy.
ipbus_out_raw_dpram	out	ipb_wbus
		IPBus access bus signal going to RAW SPY DPRAM.
ipbus_in_raw_dpram	in	ipb_rbus
		IPBus access bus signal coming from RAW SPY DPRAM.
TEST_CONTROL_REG	out	STD_LOGIC_VECTOR ( 31 downto 0 )
		Test Control Register at Top Level Readout Firmware.
link_error_flags	in	STD_LOGIC_VECTOR ( 53 downto 0 )
		54-b error flags from the Error Flag FIFO to IPBUS register
busy_raw_counter	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Busy counter for RAW data buffers.
busy_tob_counter	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Busy counter for TOB data buffers.
busy_raw_duration_counter	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Busy counter for RAW BUSY Duration.
busy_tob_duration_counter	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Busy counter for TOB BUSY duration.
ECR_debug_counter	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		ECR_debug_counter.
L1A_debug_counter	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		L1A_debug_counter.
real_time_40m_counter	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Real time 40MHz counter, counting number of 40MHz ticks.
tob_double_word_counter	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Number of identical TOB double words counter.
raw_fsm_monitor	out	std_logic_vector ( 31 downto 0 )
		Monitor RAW Readout state machines.
tob_fsm_monitor	out	std_logic_vector ( 39 downto 0 )
		Monitor TOB Readout state machines.
ttc_err_history_debug	in	std_logic_vector ( 31 downto 0 )
		History of last 8 TTC errors.
l1a_id_good_debug	in	std_logic_vector ( 31 downto 0 )
		Shows last good L1A ID.
l1a_id_err_debug	in	std_logic_vector ( 31 downto 0 )
		Shows last corrupt L1A ID.
l1a_id_expected_debug	in	std_logic_vector ( 31 downto 0 )
		Shows last expected L1A ID on error.
bcn_err_expected_debug	in	std_logic_vector ( 31 downto 0 )
		Error, bad BCN and expected BCN on BCN error.
l1id_parity_err_cntr_debug	in	std_logic_vector ( 31 downto 0 )
		Parity error count on L1A.
l1id_mismatch_cntr_debug	in	std_logic_vector ( 31 downto 0 )
		Mismatch error count on L1A.
bcn_parity_err_cntr_debug	in	std_logic_vector ( 31 downto 0 )
		Parity error count on BCN.
bcn_mismatch_cntr_debug	in	std_logic_vector ( 31 downto 0 )
		Mismatch error count on BCN.

Detailed Description

IPBUS readout slave definitions of registers used in the Top Level Readout Block.

This is the IPBUS readout slave definitions of registers used in the Top Level Readout Block. There are 3 section:

1. Top Level IPBUS Fabric and Registers.
2. RAW Calorimeter Readout Registers.
3. XTOB/TOB Readout Registers.

There are two registers at this level, therefore there is a need for a IPBUS Fabric Module.

The IPBus bus fabric, which also has address select logic and data multiplexers. This version selects the addressed slave depending on the state of incoming control lines.

The control register is a 32b register, which is read/written through the IPBus.

• bit 0 : 1 = all fibre readout, 0 = error fibre readout

The Pulse Registe is 32b register, which is read/written through the IPBus.

• This is a pulse register and automatically resets to ZERO after one clock cycle.
• bit 0 = Not Used
• bit 1 = Reset 24-bit L1A_ID counter
• bit 2 = Reset FIFOs and FSMs in RAW Readout module
• bit 3 = Reset FIFOs and FSMs in TOB Readout module
• bit 4 = Not Used
• bit 5 = Reset SPY RAM Write address to Zero for both RAW and TOB Readout
• bit 6 = Reset BUSY counter for RAW and TOB data
• bit 7 = Reset ECR Debug Counter
• bit 8 = Reset L1A Debug Counter
• bit 9 = Latch BUSY Counters for readout by TDAQ software

Top Level Counters, which are read through the IPBus.

• Addr 0 = BUSY RAW counter - Number of RAW Readout BUSY assertions
• Addr 1 = BUSY TOB counter - Number of TOB Readout BUSY assertions
• Addr 2 = BUSY RAW Duration counter - Number of 40M clocks RAW Readout BUSY is asserted
• Addr 3 = BUSY TOB Duration counter - Number of 40M clocks TOB Readout BUSY is asserted
• Addr 4 = ECR Debug Counter
• Addr 5 = L1A Debug Counter
• Addr 6 = Real Time 40M Counter - Number of 40M clocks
• Addr 7 = TOB Double Word Counter - Number of identical TOB double words

Author

Saeed Taghavi

Definition at line 57 of file readout_ipb_slave.vhd.

---

The documentation for this class was generated from the following file:

• Readout/src/readout_ipb_slave.vhd