TOBs_rdout.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library ipbus_lib;
use ipbus_lib.ipbus.all;
 
Library UNISIM;
use UNISIM.vcomponents.all;
 
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
 
library TOB_rdout_lib;
use TOB_rdout_lib.TOB_rdout_ip_pkg.ALL;
use TOB_rdout_lib.data_type_pkg.all;
 
library algolib;
use algolib.AlgoDataTypes.all;
 
entity TOBs_rdout is
    Generic
        (
    FPGA_NUMBER : integer := 1
        ) ;
    Port (
       RST                   : in std_logic ;
       hw_addr               : in STD_LOGIC_VECTOR(1 downto 0) ;
       RST_spy_mem_wr_addr         : in std_logic ;
       TOB_FIFO_sw_rst          : in std_logic ;
       XTOB_eg_512b_in        :  in AlgoXOutput;        -- array 8 x 64b words XTOB e/g
       XTOB_eg_Valid_flg_in   : in STD_LOGIC_VECTOR (7 downto 0);
       XTOB_eg_sync_in        : in STD_LOGIC;
       XTOB_tau_512b_in       :  in AlgoXOutput;        -- array 8 x 64b words XTOB tau
       XTOB_tau_Valid_flg_in  : in STD_LOGIC_VECTOR (7 downto 0);
       XTOB_tau_sync_in       : in STD_LOGIC;
       OUT_XTOB_BCN          : in std_logic_vector(6 downto 0);
       TOBs_32b_in          : in STD_LOGIC_VECTOR (31 downto 0);
       TOBs_sync_in         : in STD_LOGIC;
       TOBs_valid_flg_in    : in STD_LOGIC;
       OUT_TOB_BCN           : in std_logic_vector(6 downto 0);
       TOB_type_in          : in STD_LOGIC;
       read_on_err_in        : in  STD_LOGIC;
       clk_40M_in           : in  STD_LOGIC;
       clk_200M_in : in STD_LOGIC;
       clk_280M_in          : in  STD_LOGIC;
       TOB_TXOUTCLK         : in STD_LOGIC;
       shelf_number  : in STD_LOGIC_VECTOR (3 downto 0);
       efex_slot_num  : in STD_LOGIC_VECTOR (3 downto 0);
       L1A_in               : in  STD_LOGIC;
       BCN_ID_in            : in  STD_LOGIC_VECTOR (11 downto 0);
       L1A_ID_in            : in  STD_LOGIC_VECTOR (31 downto 0);
       TOB_ready_in          : in  std_logic ;
       TOB_out_to_MGT_is_char : out STD_LOGIC;
       TOB_out_to_MGT         : out STD_LOGIC_VECTOR (31 downto 0);
       L1A_ID_Event_out       : out STD_LOGIC_VECTOR (31 downto 0);   -- L1A ID of current event
       pre_ld_TOB_wr_addr     : in STD_LOGIC_VECTOR (8 downto 0) ;
       pre_ld_eg_XTOB_wr_addr     : in STD_LOGIC_VECTOR (8 downto 0) ;
       pre_ld_tau_XTOB_wr_addr     : in STD_LOGIC_VECTOR (8 downto 0) ;
       cntr_load_en           : in STD_LOGIC;
       DPR_locations_to_rd    : in STD_LOGIC_VECTOR (2 downto 0) ;
       trigger_slice_in       : in STD_LOGIC_VECTOR(3 downto 0) ;
       TOB_data_FIFO_flags    : out STD_LOGIC_VECTOR (31 downto 0);
       XTOB_eg_FIFO_rd_data_count          : out STD_LOGIC_VECTOR (8 downto 0);
       XTOB_eg_FIFO_pFULL_THRESH_assert  : in  STD_LOGIC_VECTOR (8 downto 0);
       XTOB_eg_FIFO_pFULL_THRESH_negate  : in  STD_LOGIC_VECTOR (8 downto 0);
       XTOB_tau_FIFO_rd_data_count         : out STD_LOGIC_VECTOR (8 downto 0);    -- occupancy of tau XTOB FIFO
       XTOB_tau_FIFO_pFULL_THRESH_assert : in  STD_LOGIC_VECTOR (8 downto 0);   -- tau XTOB FIFO
       XTOB_tau_FIFO_pFULL_THRESH_negate : in  STD_LOGIC_VECTOR (8 downto 0);   -- tau XTOB FIFO
       T_TOB_FIFO_data_count           : out STD_LOGIC_VECTOR (8 downto 0);     -- sorted TOBs FIFO occupancy count
       T_TOBs_FIFO_pFULL_THRESH_assert  : in  STD_LOGIC_VECTOR (8 downto 0);    -- TOBs FIFO
       T_TOBs_FIFO_pFULL_THRESH_negate  : in  STD_LOGIC_VECTOR (8 downto 0);    -- TOBs FIFO
       tob_busy_thresh_assert  : in  STD_LOGIC_VECTOR (8 downto 0);    -- TOBs FIFO
       tob_busy_thresh_negate  : in  STD_LOGIC_VECTOR (8 downto 0);    -- TOBs FIFO
       BCN_FIFO_pFULL_THRESH_assert             : in  std_logic_vector(8 downto 0);
       BCN_FIFO_pFULL_THRESH_negate             : in  std_logic_vector(8 downto 0);
       BCN_FIFO_TOB_rd_data_count         : out STD_LOGIC_VECTOR (8 downto 0);   -- occupancy of BCN & L1A FIFO for RAW Readout
       Link_output_FIFO_pFULL_THRESH_assert   : in  STD_LOGIC_VECTOR (12 downto 0);   -- Link_output_FIFO
       Link_output_FIFO_pFULL_THRESH_negate   : in  STD_LOGIC_VECTOR (12 downto 0);   -- Link_output_FIFO
       Link_output_FIFO_rd_data_count         : out STD_LOGIC_VECTOR (12 downto 0);   -- occupancy of TOB output link MGT FIFO
       SPY_TOB_mem_wr_addr        : out STD_LOGIC_VECTOR (10 downto 0);   -- SPY memory wr_addr (read only)
       ipb_clk                : in std_logic ;
       ipbus_out_tob_dpram    : out ipb_rbus;
       ipbus_in_tob_dpram     : in  ipb_wbus;
       busy_tob          : out std_logic;
       sync_280m_out   : out STD_LOGIC;
       tob_double_word_en   : out STD_LOGIC;
       tob_fsm_monitor   : out std_logic_vector (39 downto 0)
       );
    end TOBs_rdout;
 
architecture RTL of TOBs_rdout is
 
--************************** Register Declarations ****************************
    signal  RST_i               : STD_LOGIC;
    signal  TOB_FIFO_sw_rst_i   : STD_LOGIC ;
    signal  clk_in_280M_i       : STD_LOGIC;
    signal  rdout_T_TOB_209b_i  : STD_LOGIC_VECTOR (208 downto 0);  -- T_TOBs 209b = 7b TOB_BCN +4b error+6b valid +192b TOB data
 
    signal  T_TOB_full_i        : STD_LOGIC;
    signal  T_TOB_empty_i       : STD_LOGIC;
    signal  T_TOB_valid_i       : STD_LOGIC;
    signal  T_TOB_prog_full_i   : STD_LOGIC;
    signal  T_TOB_FIFO_data_count_i :  STD_LOGIC_VECTOR (8 downto 0);     -- occupancy of sorted TOB FIFO
    signal  XTOB_eg_FIFO_rd_data_count_i  :  STD_LOGIC_VECTOR (8 downto 0);     -- occupancy of sorted TOB FIFO
    signal  tob_data_mgt_fsm_i, tob_data_mux_fsm_i, tob_data_dpram_fsm_i  :  STD_LOGIC_VECTOR (7 downto 0);
    signal  xtob_eg_data_dpram_fsm_i, xtob_tau_data_dpram_fsm_i  :  STD_LOGIC_VECTOR (7 downto 0);
 
    signal  DPR_XTOBs_eg_in_i       : array_8_of_252b;  -- XTOBs {array 8 of [(5*48b) + 5b valid] + XTOB_BCN}
    signal  DPR_XTOBs_eg_out_i      : array_8_of_252b;  -- XTOBs {array 8 of [(5*48b) + 5b valid] + XTOB_BCN}
 
    signal  DPR_XTOBs_tau_in_i      : array_8_of_252b;  -- XTOBs {array 8 of [(5*48b) + 5b valid] + XTOB_BCN}
    signal  DPR_XTOBs_tau_out_i     : array_8_of_252b;  -- XTOBs {array 8 of [(5*48b) + 5b valid] + XTOB_BCN}
 
    signal  TOB_ready_i             : std_logic ;
 
    signal  L1A_rd_en_i             : std_logic ;
 
    signal  pre_ld_wr_addr_TOB_i    : STD_LOGIC_VECTOR (8 downto 0);
    signal  DPR_locations_to_rd_i   : STD_LOGIC_VECTOR (2 downto 0);
 
    signal  FIFO_rd_en_i            : std_logic := '0' ;
    signal  rdout_XTOB_eg_i         : array_8_of_252b;  -- XTOBs {array 8 of [(5*48b) + 5b valid] + XTOB_BCN}
    signal  rdout_XTOB_tau_i        : array_8_of_252b;  -- XTOBs {array 8 of [(5*48b) + 5b valid] + XTOB_BCN}
    signal  valid_XTOBs_eg_i        : STD_LOGIC;
    signal  valid_XTOBs_tau_i       : STD_LOGIC;
    signal  frame_cntr_en_i         : std_logic;
    signal  frame_cntr_en_ii        : std_logic;
    signal  pre_ld_wr_addr_XTOB_eg_i    : STD_LOGIC_VECTOR (8 downto 0);
    signal  pre_ld_wr_addr_XTOB_tau_i   : STD_LOGIC_VECTOR (8 downto 0);
 
    signal  XTOB_eg_full_i          : std_logic;
    signal  XTOB_eg_empty_i         : std_logic;
    signal  XTOB_eg_prog_full_i     : std_logic;
 
    signal  XTOB_tau_full_i          : std_logic;
    signal  XTOB_tau_empty_i         : std_logic;
    signal  XTOB_tau_prog_full_i     : std_logic;
 
    signal  TOB_empty_flag_i        : std_logic;
    signal  TOB_pfull_flag_i        : std_logic;
    signal  TOB_out_valid_i         : STD_LOGIC;
    signal  TOB_out_is_char_i       : STD_LOGIC;
    signal  TOBs_out_i              :  STD_LOGIC_VECTOR (31 downto 0);  -- TOBs 32b out to FIFO
    signal  FIFO_TOBs_in_i          :  STD_LOGIC_VECTOR (32 downto 0);
    signal  Link_output_FIFO_TOBs_out_i   :  STD_LOGIC_VECTOR (32 downto 0);
    signal  TOB_out_to_MGT_i              :  STD_LOGIC_VECTOR (31 downto 0);  -- TOBs 32b out to MGT
    signal  TOB_out_to_MGT_1dly           :  STD_LOGIC_VECTOR (31 downto 0);  -- TOBs 32b out to MGT
    signal  TOB_data_out_MGT_i            :  STD_LOGIC_VECTOR (31 downto 0);  -- TOBs 32b out to MGT
    signal  Link_output_FIFO_rd_en_i, TOB_out_to_MGT_is_char_i,TOB_out_to_MGT_is_char_1dly : STD_LOGIC;
    signal  Link_output_FIFO_TOB_valid_i                : STD_LOGIC;
    signal  T_TOB_out_valid_i     : STD_LOGIC;
    signal  T_TOB_out_valid_1dly  : STD_LOGIC;
    signal  TOB_out_char_MGT_i    : STD_LOGIC;
 
    signal  Link_output_FIFO_full       : std_logic;
    signal  Link_output_FIFO_empty      : std_logic;
    signal  Link_output_FIFO_prog_full  : std_logic;
    signal  Link_output_FIFO_prog_empty : std_logic;
 
    signal  TOB_data_FIFO_flags_i   : STD_LOGIC_VECTOR (31 downto 0);
 
    signal  reg1, reg2              : std_logic := '0' ;
    signal  frame_cntr_dec_en_i     : std_logic;
    signal  frame_counter_dec_en_i  : std_logic := '0' ;
    signal  frame_count_i           :  STD_LOGIC_VECTOR (11 downto 0);      -- Frame counter
 
    signal  TOB_safe_mode_i           : std_logic;
    signal  tob_busy_assert_i         : std_logic;
 
    signal  SPY_TOB_mem_wr_addr_i      :  STD_LOGIC_VECTOR (10 downto 0) ;
    signal  SPY_TOB_mem_wr_addr_en_i   : STD_LOGIC ;
    signal  SPY_FIFO_TOB_in_i          : STD_LOGIC_VECTOR (35 downto 0) ;
    signal  SPY_TOB_mem_rd_data_i      : STD_LOGIC_VECTOR (35 downto 0) ;
    signal  enable_tob_spy_mem_wr      : std_logic ;
    signal  tst_fsm_cntr_i, q1_int             : STD_LOGIC_VECTOR (31 downto 0) ;
 
    signal  BCN_FIFO_rd_en_i        : std_logic  ;
    signal  BCN_FIFO_full_i         : std_logic ;
    signal  BCN_FIFO_empty_i        : std_logic ;
    signal  BCN_FIFO_valid_i        : std_logic ;
    signal  BCN_FIFO_prog_full_i    : std_logic ;
    signal  BCN_FIFO_Data_in_i      : STD_LOGIC_VECTOR(46 downto 0) ;
    signal  BCN_FIFO_Data_in_1dly   : STD_LOGIC_VECTOR(46 downto 0) ;
    signal  BCN_FIFO_Data_out_i     : STD_LOGIC_VECTOR(46 downto 0) ;
 
    signal  FIFO_BCN_in_i           : STD_LOGIC_VECTOR(11 downto 0) ;
    signal  FIFO_L1A_ID_i           : STD_LOGIC_VECTOR(23 downto 0) ;
    signal  FIFO_L1A_ID_EXT_i       : STD_LOGIC_VECTOR(7 downto 0) ;
    signal  LO_FIFO_rd_data_count_i : STD_LOGIC_VECTOR(12 downto 0) ;
    signal  LO_FIFO_wr_data_count_i : STD_LOGIC_VECTOR(12 downto 0) ;
    signal  busy_tob_i              :  std_logic;  -- tob data busy out to control FPGA
    signal  L1A_in_1dly, L1A_in_2dly, L1A_in_3dly  :  std_logic;
    signal  read_on_err_i           :  std_logic;
    signal  sync_280m_i             :  std_logic;
    signal  SPY_mem_wr_addr_tc_i    :  std_logic;
 
--------------------------------
 
--  ####### attributes  ########
 attribute TIG       : string ;
 attribute TIG of L1A_in_1dly : signal is "true" ;
 attribute TIG of TOB_FIFO_sw_rst_i : signal is "true" ;
 
 attribute keep       : string ;
 attribute max_fanout : integer;
 attribute keep of       TOB_FIFO_sw_rst_i : signal is "true" ;
 attribute max_fanout of TOB_FIFO_sw_rst_i : signal is 40;
 attribute keep of       FIFO_rd_en_i : signal is "true" ;
 attribute max_fanout of FIFO_rd_en_i : signal is 40;
 attribute keep of       BCN_FIFO_empty_i : signal is "true" ;
 attribute max_fanout of BCN_FIFO_empty_i : signal is 25;
 attribute keep of       BCN_FIFO_prog_full_i : signal is "true" ;
 attribute max_fanout of BCN_FIFO_prog_full_i : signal is 25;
 attribute keep of       BCN_FIFO_full_i : signal is "true" ;
 attribute max_fanout of BCN_FIFO_full_i : signal is 25;
 
--   #######################################
 
begin
 
    clk_in_280M_i   <= clk_280M_in ;
 
    -- input signals
 
    RST_i           <= RST ;
    pre_ld_wr_addr_TOB_i    <= pre_ld_TOB_wr_addr ;     -- latency pre load for DRP wr address
    DPR_locations_to_rd_i   <= DPR_locations_to_rd ;    -- number of DRP locations to wr into FIFO 1 to 5
 
    TOB_FIFO_sw_rst_i        <= RST_i OR TOB_FIFO_sw_rst ; -- rst by s/w or RST
 
    busy_tob  <=  busy_tob_i ;  -- tob data busy out to control FPGA
 
    -- output signals
    -- FIFO flags assignments
    TOB_data_FIFO_flags <= TOB_data_FIFO_flags_i;
 
    TOB_data_FIFO_flags_i(0) <= T_TOB_empty_i   ;
    TOB_data_FIFO_flags_i(1) <= T_TOB_prog_full_i  ;
    TOB_data_FIFO_flags_i(2) <= T_TOB_full_i ;
 
    TOB_data_FIFO_flags_i(3) <= XTOB_eg_empty_i   ;
    TOB_data_FIFO_flags_i(4) <= XTOB_eg_prog_full_i ;
    TOB_data_FIFO_flags_i(5) <= XTOB_eg_full_i ;
 
    TOB_data_FIFO_flags_i(6) <= XTOB_tau_empty_i  ;
    TOB_data_FIFO_flags_i(7) <= XTOB_tau_prog_full_i ;
    TOB_data_FIFO_flags_i(8) <= XTOB_tau_full_i ;
 
    TOB_data_FIFO_flags_i(9)  <= Link_output_FIFO_empty  ;
    TOB_data_FIFO_flags_i(10) <= Link_output_FIFO_prog_full ;
    TOB_data_FIFO_flags_i(11) <= Link_output_FIFO_full ;
 
    TOB_data_FIFO_flags_i(12) <= BCN_FIFO_empty_i   ;
    TOB_data_FIFO_flags_i(13) <= BCN_FIFO_prog_full_i  ;
    TOB_data_FIFO_flags_i(14) <= BCN_FIFO_full_i ;
 
    TOB_data_FIFO_flags_i(15) <= TOB_safe_mode_i ;  -- Safe Mode operation flag for TOB readout
    TOB_data_FIFO_flags_i(16) <= TOB_ready_i ;      -- Ready signal from control FPGA for TOB readout
    TOB_data_FIFO_flags_i(17) <= busy_tob_i ;       -- BUSY signal from proc FPGA to stop L1A signal
    TOB_data_FIFO_flags_i(31 downto 18) <= (others => '0');
    
    BCN_FIFO_Data_in_i <= "000" & BCN_ID_in & L1A_ID_in ; -- write L1A number and BC number into FIFO
 
    SPY_TOB_mem_wr_addr      <= SPY_TOB_mem_wr_addr_i ; -- SPY memory address fo iPus Readout register
 
    T_TOB_FIFO_data_count   <= T_TOB_FIFO_data_count_i;
    XTOB_eg_FIFO_rd_data_count <= XTOB_eg_FIFO_rd_data_count_i;
 
    TOB_out_to_MGT          <=  TOB_data_out_MGT_i;         -- event TOBs to MGT
    TOB_out_to_MGT_is_char  <=  TOB_out_char_MGT_i;  -- TOB data is char
    L1A_ID_Event_out <= FIFO_L1A_ID_EXT_i & FIFO_L1A_ID_i ; -- 8b L1A ID Extended + 24b L1A ID of the current event
    sync_280m_out <= sync_280m_i;      -- this is 1 in 7 sync'ed to 40M clk
 
    tob_fsm_monitor <= tob_data_mgt_fsm_i & tob_data_mux_fsm_i & xtob_tau_data_dpram_fsm_i & xtob_eg_data_dpram_fsm_i & tob_data_dpram_fsm_i ;
 
 
-- This module generates a synch signal synchronised to 40MHz and 280MHz clocks
-- one synch pulse is generated - this is 1 in 7 sync'ed to 40M clock
  U1_gen_sync_280 : entity TOB_rdout_lib.gen_sync_280M
    port map(
      RST           => RST_i,           -- RST from 40MHz MMCM lock signal
      clk_40M       => clk_40M_in,   -- Clock 40MHz
      clk_280M      => clk_in_280M_i,
      sync_280m_out => sync_280m_i      -- this is 1 in 7 sync'ed to 40M clk
      );
 
-- This FDCE regitsters the cFPGA Ready input signal to receive TOB/XTOB Event Data.
U0_FDCE_xoff : FDCE
   generic map (
      INIT => '0') -- Initial value of register ('0' or '1')
   port map (
      Q    => TOB_ready_i,      -- Data output
      C    => clk_in_280M_i,      -- Clock input
      CE   => '1',    -- Clock enable input
      CLR  => '0' ,
      D    => TOB_ready_in   -- Ready signal from control FPGA
   );
 
-- the FSM regitsters occupancy of XTOB data FIFO to send TOB BUSY signal to cFPGA
U0_busy_flag_fsm : entity TOB_rdout_lib.busy_flag_fsm
    generic map (
        width => 9
        )
    port map (
       clk => clk_in_280M_i,
       rst => TOB_FIFO_sw_rst_i,
       busy_flag_assert => tob_busy_thresh_assert,
       busy_flag_negate => tob_busy_thresh_negate,
       fifo_data_count  => XTOB_eg_FIFO_rd_data_count_i,   -- use XTOBs FIFO Data instead of TOBs so U3 & U4 can assert BUSY as well
       busy_flag => busy_tob_i
    );
 
 
---- Pipelines process
--U0_proc1 : process (clk_40M_in)
--    begin
--        if rising_edge (clk_40M_in) then
--            BCN_FIFO_Data_in_i <= "000" & BCN_ID_in & L1A_ID_in ; -- write L1A number and BC number into FIFO
--            L1A_in_1dly  <= L1A_in;                -- delay by 1 clock to aligh with read_on_err_in
--        end if;
--    end process;
 
---- Pipelines process
--U0_proc2 : process (clk_in_280M_i)
--    begin
--        if rising_edge (clk_in_280M_i) then
--            BCN_FIFO_Data_in_1dly <= "00" & read_on_err_in & BCN_FIFO_Data_in_i(43 downto 0);    -- delay by 1 clock to aligh with read_on_err_in
--            L1A_in_2dly <= L1A_in_1dly AND sync_280m_i;  -- delay by 1 clock to aligh with read_on_err_in
--            L1A_in_3dly <= L1A_in_2dly;                  -- delay by 1 clock to aligh with read_on_err_in
--        end if;
--    end process;
 
 
-- This is TTC FIFO for TOB/XTOB Readour, which stores the following values:.
-- bits 46:44 = not used
-- bits 43:32 = Bunch Crossing Number - generated in pFPGA
-- bits 31:24 = Extended L1A - received from CFPGA
-- bits 23:0  = L1A_ID - received from cFPGA
--
U0_FIFO_BCN_L1A : FIFO_47b_512          -- the flags from this FIFO is used
    PORT MAP (
      rst           => TOB_FIFO_sw_rst_i,   -- sys RST OR RAW_FIFO_sw_rst
      wr_clk        => clk_40M_in,          -- clk_40M_in,
      rd_clk        => clk_in_280M_i,
      din           => BCN_FIFO_Data_in_i ,
      wr_en         => L1A_in,      -- write only on rising edge of L1A
      rd_en         => BCN_FIFO_rd_en_i,
      dout          => BCN_FIFO_Data_out_i,     -- BCN + EXT_L1A_ID + L1A_ID  44b = 12b + 8b + 24b
      valid         => BCN_FIFO_valid_i ,
      rd_data_count => BCN_FIFO_TOB_rd_data_count,
      prog_full_thresh_assert => BCN_FIFO_pFULL_THRESH_assert,    --  9b
      prog_full_thresh_negate => BCN_FIFO_pFULL_THRESH_negate,
      prog_full     => BCN_FIFO_prog_full_i,
      full          => BCN_FIFO_full_i,
      empty         => BCN_FIFO_empty_i
    );
 
    FIFO_L1A_ID_i       <= BCN_FIFO_Data_out_i(23 downto 0) ;   -- 24b L1A ID
    FIFO_L1A_ID_EXT_i   <= BCN_FIFO_Data_out_i(31 downto 24) ;  -- 8b L1A ID Extended
    FIFO_BCN_in_i       <= BCN_FIFO_Data_out_i(43 downto 32) ;  -- 12b BCN ID
    read_on_err_i       <= BCN_FIFO_Data_out_i(44);             -- Read RAW data on error flag
 
-- This T_TOBs_sorting module receives 7 x 32-bit TOBs together with 7 valid signals in series,
-- and sorts them into a 6 x 32-bit parallel word and 6 bit valid word to store in Circular DPRAM.
-- The 7th TOB is ignored as a trailer is added to transfer the data to TOPO.
-- In order to be able to read multi-slices, the TOBs and XTOBs must be converted into long parallel data words.
--
-- This module is only instanstiated for Process FPGA 1 and 2, and is disabled for Process FPGA 3 and 4.
-- Only Process FPGA 1 and 2 transmit e/g and tau events to TOPO, and the off-line Readout,
-- but Process FPGA 3 and 4 do not transmit to TOPO instead they send their TOBs to Process FPGA 1 and 2.
-- Process FPGA 3 and 4 transmit XTOB only events to the Control FPGA.
--
-- output signals:
-- If Process FPGA 1 & 2, then assign the outputs to TOBs data
-- If Process FPGA 3 & 4, then assign the outputs to ZERO, no TOB data in these FPGAs
 
U1_TOB_sorting_gen : if FPGA_NUMBER = 1 or FPGA_NUMBER = 2 generate
 
    U1_TOBs_sorting :  entity TOB_rdout_lib.T_TOBs_sorting
        generic map(FPGA_NUMBER => FPGA_NUMBER)
        Port map (
            L1A_in                 =>  L1A_in,
            TOB_FIFO_sw_rst        =>  TOB_FIFO_sw_rst_i ,  -- RST OR TOB_FIFO_sw_rst
            TOBs_32b_in            =>  TOBs_32b_in ,        -- sorted TOBs 32b * 7 is series
            TOBs_sync_in           =>  TOBs_sync_in ,       -- sorted TOB start signal
            TOBs_valid_flg_in      =>  TOBs_valid_flg_in,   -- sorted TOB write signal
            ALGO_TOB_BCN_in        =>  OUT_TOB_BCN,         -- sorted TOB BC_ID with delay through ALGO/sorting block
            FIFO_rd_en             =>  FIFO_rd_en_i ,
            clk_280M_in            =>  clk_in_280M_i,
            pre_ld_wr_addr_TOB     =>  pre_ld_wr_addr_TOB_i,
            DPR_locations_to_rd    =>  DPR_locations_to_rd_i,    -- number of DRP locations to read 1 to 5
            trigger_slice_in       => trigger_slice_in ,          -- i/p Trigger slice number - on L1A
            TOBs_FIFO_pFULL_THRESH_assert   => T_TOBs_FIFO_pFULL_THRESH_assert,   -- connect to relevant register
            TOBs_FIFO_pFULL_THRESH_negate   => T_TOBs_FIFO_pFULL_THRESH_negate,   -- connect to relevant register
            rdout_T_TOB_209b       =>  rdout_T_TOB_209b_i,       -- sorted TOBs FIFO o/p 209b = 7b TOB_BCN +4b error+6b valid +192b TOB data
            TOBs_FIFO_data_count   =>  T_TOB_FIFO_data_count_i ,   -- sorted TOBs FIFO occupancy count
            TOBs_data_valid        =>  T_TOB_valid_i,
            TOBs_data_full         =>  T_TOB_full_i,
            TOBs_data_empty        =>  T_TOB_empty_i,
            TOBs_data_prog_full    =>  T_TOB_prog_full_i,
            tob_data_dpram_fsm     =>  tob_data_dpram_fsm_i
            );
    else generate
       rdout_T_TOB_209b_i     <= (others => '0');
       T_TOB_FIFO_data_count_i  <= (others => '0') ;
       T_TOB_full_i           <= '0';
       T_TOB_empty_i          <= '1'; -- show emppty flag
       T_TOB_valid_i          <= '0';
       T_TOB_prog_full_i      <= '0';
       tob_data_dpram_fsm_i   <= (others => '0');
    end generate U1_TOB_sorting_gen;
 
 
    pre_ld_wr_addr_XTOB_eg_i <= pre_ld_eg_XTOB_wr_addr ; -- set correct value register in XML
 
-- This is the XTOB e/g sorting module.
-- It receives 20 x 64-bit TOBs together with 40 valid signal in series,
-- and sorts them into a 80 x 32-bit parallel word and 40 bit valid word to store in Circular DPRAM.
 
U2_XTOBs_eg_sorting :  entity TOB_rdout_lib.XTOBs_sorting
    generic map(FPGA_NUMBER => FPGA_NUMBER)
    Port map (
        L1A_in                 =>  L1A_in,
        XTOB_FIFO_sw_rst    =>  TOB_FIFO_sw_rst_i,       -- RST OR TOB_FIFO_sw_rst
        XTOB_512b_in        =>  XTOB_eg_512b_in,          --  XTOB e/g  data in 64b * 8
        XTOB_Valid_flg_in   =>  XTOB_eg_Valid_flg_in,     -- 8b XTOB e/g has valid data
        XTOB_sync_in        =>  XTOB_eg_sync_in,          -- XTOB e/g  sync signal
        ALGO_XTOB_BCN_in     =>  OUT_XTOB_BCN,         -- sorted TOB BCN with delay through ALGO/sorting block
        pre_ld_wr_addr_XTOB  =>  pre_ld_wr_addr_XTOB_eg_i,
        DPR_locations_to_rd  =>  DPR_locations_to_rd_i,    -- number of DRP locations to read 1 to 5
        trigger_slice_in     => trigger_slice_in ,         -- i/p Trigger slice number - on L1A
        FIFO_rd_en           =>  FIFO_rd_en_i ,
        clk_200M_in          =>  clk_200M_in   ,       -- i/p
        clk_280M_in          =>  clk_in_280M_i,
        XTOB_FIFO_pFULL_THRESH_assert => XTOB_eg_FIFO_pFULL_THRESH_assert ,
        XTOB_FIFO_pFULL_THRESH_negate => XTOB_eg_FIFO_pFULL_THRESH_negate ,
        FIFO_XTOB_data_out      =>  rdout_XTOB_eg_i,            -- e/g XTOBs output of fifo - XTOBs (5*48b) + 5b valid + 7b XTOB_BCN
        XTOB_FIFO_rd_data_count =>  XTOB_eg_FIFO_rd_data_count_i ,   -- occupancy of e/g XTOB FIFO - RD clk
        XTOB_FIFO_valid         =>  valid_XTOBs_eg_i,
        XTOB_FIFO_full          =>  XTOB_eg_full_i,
        XTOB_FIFO_empty         =>  XTOB_eg_empty_i,
        XTOB_FIFO_prog_full     =>  XTOB_eg_prog_full_i,
        xtob_data_dpram_fsm     =>  xtob_eg_data_dpram_fsm_i
        );
 
    pre_ld_wr_addr_XTOB_tau_i <= pre_ld_tau_XTOB_wr_addr ; -- set correct value register in XML
 
-- This is the XTOB tau sorting module.
-- It receives 20 x 64-bit TOBs together with 40 valid signal in series,
-- and sorts them into a 80 x 32-bit parallel word and 40 bit valid word to store in Circular DPRAM.
 
U3_XTOBs_tau_sorting :  entity TOB_rdout_lib.XTOBs_sorting
    generic map(FPGA_NUMBER => FPGA_NUMBER)
    Port map (
        L1A_in                 =>  L1A_in,
        XTOB_FIFO_sw_rst    =>  TOB_FIFO_sw_rst_i,   -- RST OR TOB_FIFO_sw_rst
        XTOB_512b_in        =>  XTOB_tau_512b_in,   --  XTOB e/g  data in 64b * 8
        XTOB_Valid_flg_in   =>  XTOB_tau_Valid_flg_in,     -- 8b XTOB e/g has valid data (x 5)
        XTOB_sync_in        =>  XTOB_tau_sync_in,     -- XTOB e/g  sync signal
        ALGO_XTOB_BCN_in     =>  OUT_XTOB_BCN,         -- sorted TOB BCN with delay through ALGO/sorting block
        pre_ld_wr_addr_XTOB  =>  pre_ld_wr_addr_XTOB_tau_i,
        DPR_locations_to_rd  =>  DPR_locations_to_rd_i,    -- number of DRP locations to read 1 to 5
        trigger_slice_in     => trigger_slice_in ,         -- i/p Trigger slice number - on L1A
        FIFO_rd_en           =>  FIFO_rd_en_i ,
        clk_200M_in          =>  clk_200M_in   ,       -- i/p
        clk_280M_in          =>  clk_in_280M_i,
        XTOB_FIFO_pFULL_THRESH_assert => XTOB_tau_FIFO_pFULL_THRESH_assert ,
        XTOB_FIFO_pFULL_THRESH_negate => XTOB_tau_FIFO_pFULL_THRESH_negate ,
        FIFO_XTOB_data_out      =>  rdout_XTOB_tau_i  ,         -- XTOBs tau output of fifo - XTOBs (5*48b) + 5b valid + 7b XTOB_BCN
        XTOB_FIFO_rd_data_count =>  XTOB_tau_FIFO_rd_data_count ,  -- occupancy of tau XTOB FIFO -  RD clk
        XTOB_FIFO_valid         =>  valid_XTOBs_tau_i,
        XTOB_FIFO_full          =>  XTOB_tau_full_i,
        XTOB_FIFO_empty         =>  XTOB_tau_empty_i,
        XTOB_FIFO_prog_full     =>  XTOB_tau_prog_full_i,
        xtob_data_dpram_fsm     =>  xtob_tau_data_dpram_fsm_i
        );
 
--gen_empty_flags : if (FPGA_NUMBER = 1 OR FPGA_NUMBER = 2) generate
--        TOB_empty_flag_i   <= XTOB_eg_empty_i OR XTOB_tau_empty_i OR T_TOB_empty_i OR BCN_FIFO_empty_i ; -- all must not be empty to prevent a read from empty FIFO
--        TOB_pfull_flag_i   <= XTOB_eg_prog_full_i OR XTOB_tau_prog_full_i OR T_TOB_prog_full_i ;    -- one flag can be pFULL
--    else generate
        TOB_empty_flag_i   <= XTOB_eg_empty_i OR XTOB_tau_empty_i OR BCN_FIFO_empty_i ; -- all must not be empty to prevent a read from empty FIFO
        TOB_pfull_flag_i   <= XTOB_eg_prog_full_i OR XTOB_tau_prog_full_i ; -- one flag can be pFULL
--end generate gen_empty_flags;
 
 
-- Generate FSM to write TOBs and XTOBS into an event packet for pFPGA 1 and 2
-- Else Generate FSM to write only XTOBS into an event packet for pFPGA 3 and 4
 
    U6_rd_mux_fsm :  entity TOB_rdout_lib.fsm_TOBs_to_muxPISO
        generic map(FPGA_NUMBER => FPGA_NUMBER)
        PORT map (
            TOB_FIFO_sw_rst            => TOB_FIFO_sw_rst_i,    -- RST OR TOB_FIFO_sw_rst
            hw_addr                    => hw_addr ,             -- FPGA number
            trigger_slice_in           => trigger_slice_in ,     -- Trigger slice number - on L1A
            rdout_T_TOB_209b_in        => rdout_T_TOB_209b_i,   -- sorted TOBs FIFO o/p 209b = 7b TOB_BCN +4b error+6b valid +192b TOB data
            valid_T_TOB_in             => T_TOB_valid_i ,       -- indicated input sorted TOB data is valid
            TOB_type_in                => TOB_type_in ,         -- TOB Type 0 = e/g, 1 = tau
            XTOBs_eg_in                => rdout_XTOB_eg_i ,     -- XTOBs (5*48b) + 5b valid + 7b XTOB_BCN
            valid_XTOBs_eg_in          => valid_XTOBs_eg_i,
            XTOBs_tau_in               => rdout_XTOB_tau_i ,    -- XTOBs (5*48b) + 5b valid + 7b XTOB_BCN
            valid_XTOBs_tau_in         => valid_XTOBs_tau_i ,
            clk_280M_in                => clk_in_280M_i ,
            shelf_number               => shelf_number,   -- i/p shelf address
            efex_slot_num              => efex_slot_num,  -- i/p slot address
            TOB_FIFO_empty_in          => TOB_empty_flag_i ,
            DPR_locations_to_rd        => DPR_locations_to_rd_i ,   -- number of DRP locations to read 1 to 5
            TOB_prog_full_flag_in      => TOB_pfull_flag_i,
            read_on_err_in             => read_on_err_i ,   -- RAW readout expected upon Error flag
            FIFO_BCN_in                => FIFO_BCN_in_i ,   -- 12b BCN ID from counter
            FIFO_L1A_ID                => FIFO_L1A_ID_i ,   -- 24b L1A ID from TTC info
            FIFO_L1A_ID_EXT            => FIFO_L1A_ID_EXT_i ,   -- 8b L1A ID Extended from TTC info
            BCN_FIFO_valid_in          => BCN_FIFO_valid_i ,    -- data from TTC FIFO is valid
            BCN_FIFO_prog_full_in      => BCN_FIFO_prog_full_i,
            LO_FIFO_prog_full_in       => Link_output_FIFO_prog_full,
            LO_FIFO_data_count_in      => LO_FIFO_wr_data_count_i,  -- uses the 280 MHz wr clock of LO FIFO
            frame_cntr_en              => frame_cntr_en_i ,         -- enable frame counter count up
            BCN_FIFO_rd_en_out         => BCN_FIFO_rd_en_i ,        -- rd enabto BCN & L1A FIFO
            TOB_rdout_fifo_rd_en_out   => FIFO_rd_en_i ,            -- rd enable to TOB & XTOB FIFOs
            TOB_out_valid              => TOB_out_valid_i ,         -- sorted TOBs data valid to U7_Link_output_FIFO
            TOB_out_is_char            => TOB_out_is_char_i,        -- sorted TOBs is CHAR to U7_Link_output_FIFO
            TOBs_out                   => TOBs_out_i,               -- sorted TOBs valid to U7_Link_output_FIFO
            TOB_safe_mode_out          => TOB_safe_mode_i,           -- Safe Mode operation flag for TOB readout
            tob_data_mux_fsm           => tob_data_mux_fsm_i
            );
 
    FIFO_TOBs_in_i <= TOB_out_is_char_i & TOBs_out_i;  -- 1b char and 32b data
 
-- This is TOB/XTOB Link Output FIFO, which stores complete TOB/XTOB events (frames) ready to be transmitted to cFPGA via an MGT link at 11.2Gbps.
-- The output of FIFO is 32-bit data word, and 1-bit data is CHAR, which goes directly to MGT under FSM control.
--
-- The Frames are only transmitted when cFPGA indicates it is ready to receive data by setting ctrl_TOB_ready signal to 1.
-- If ctrl_TOB_ready signal is set to 0 by cFPGA, this indicates cFPGA is not ready to receive data,
-- in this case events accumulate in Link Output FIFO until occupancy reaches a pre-define level of prog_FULL,
-- at this time, Link Output FIFO stops receiving data.
--
-- Writing to LO FIFO is controlled by fsm_TOBs_to_muxPISO (OR fsm_XTOBs_to_muxPISO) FSM
-- Reading from LO FIFO is controlled by FIFO_to_MGT_TOB_FSM FSM
 
U7_Link_output_FIFO : FIFO_33b_8192
    PORT MAP (
        wr_rst      => TOB_FIFO_sw_rst_i,   -- RST OR TOB_FIFO_sw_rst
        wr_clk      => clk_in_280M_i,
        din         => FIFO_TOBs_in_i,
        wr_en       => TOB_out_valid_i,
        rd_rst      => TOB_FIFO_sw_rst_i,   -- RST OR TOB_FIFO_sw_rst
        rd_clk      => TOB_TXOUTCLK,   -- 280M clk to rd data to cntl FPGA
        rd_en       => Link_output_FIFO_rd_en_i,
        dout        => Link_output_FIFO_TOBs_out_i,
        full        => Link_output_FIFO_full,   -- on wr clk 280MHz
        empty       => Link_output_FIFO_empty,  -- on rd clk TXOUTCLK
        prog_full   => Link_output_FIFO_prog_full,
        valid       => Link_output_FIFO_TOB_valid_i,
        prog_full_thresh_assert     => Link_output_FIFO_pFULL_THRESH_assert ,
        prog_full_thresh_negate     => Link_output_FIFO_pFULL_THRESH_negate ,
        wr_data_count => LO_FIFO_wr_data_count_i  , -- wr data on wr clk 280MHz
        rd_data_count => LO_FIFO_rd_data_count_i    -- rd data on rd clk TXOUTCLK
    );
 
    Link_output_FIFO_rd_data_count <= LO_FIFO_rd_data_count_i;
 
-- This FSM reads TOB/XTOB frames from Link Output FIFO and writes into MGT to transmit to cFPGA.
-- This FSM handles one full frame at a time without pausing.
-- It monitors the TOB frame counter to find out if there are Frames waiting to be transmitted to cFPGA.
-- The Frames are only transmitted when cFPGA indicates it is ready to receive data by setting ctrl_TOB_ready signal to 1.
-- If ctrl_TOB_ready signal is set to 0 by cFPGA, this indicates cFPGA is not ready to receive data,
-- in this case events accumulate in Link Output FIFO until occupancy reaches a pre-define prog_FULL level,
-- at this time, Link Output FIFO stops receiving data.
 
U8_TOB_Link_output_FIFO_FSM : entity TOB_rdout_lib.FIFO_to_MGT_TOB_FSM
    Port map (
       TOB_FIFO_sw_rst          =>  TOB_FIFO_sw_rst_i,  -- RST OR TOB_FIFO_sw_rst
       clk_in_280M              =>  TOB_TXOUTCLK,      -- 280MHz
       ctrl_TOB_ready_in        =>  TOB_ready_i ,
       frame_counter            =>  frame_count_i,
       FIFO_MGT_TOBs            =>  Link_output_FIFO_TOBs_out_i,
       FIFO_MGT_TOB_valid       =>  Link_output_FIFO_TOB_valid_i ,
       MGT_FIFO_empty           =>  Link_output_FIFO_empty,
       FIFO_MGT_rd_en           =>  Link_output_FIFO_rd_en_i,   -- output
       frame_counter_dec_en     =>  frame_cntr_dec_en_i,
       T_TOBs_out               =>  TOB_out_to_MGT_i,         -- event TOBs to MGT
       T_TOB_is_char            =>  TOB_out_to_MGT_is_char_i,  -- TOB data is char
       T_TOB_out_valid          =>  T_TOB_out_valid_i,
       tob_data_mgt_fsm         =>  tob_data_mgt_fsm_i
       );
 
-- If the counter is ZERO, no data is available to be send to cFPGA.
 
U9_clk_closs_pulse : entity TOB_rdout_lib.clk_closs_pulse_fsm
    Port map (
       clk_src    =>  clk_in_280M_i ,
       rst_src    =>  TOB_FIFO_sw_rst_i , -- RST OR TOB_FIFO_sw_rst
       pulse_src  =>  frame_cntr_en_i,    -- input from fsm_TOBs_to_muxPISO
       clk_dest   =>  TOB_TXOUTCLK ,
       pulse_dest =>  frame_cntr_en_ii
       );
 
-- The TOB_frame_counter is a 12-bit generic up/down counter to count the number of complete Frames in Link Output FIFO to be transmitted to cFPGA.
-- When one complete Frame (event) is written to LO FIFO, this counter is incremented.
-- When one complete Frame (event) is read out LO FIFO, this counter is decremented.
-- If the counter is ZERO, no data is available to be send to cFPGA.
 
U9_frame_counter : entity TOB_rdout_lib.cntr_up_dn_generic
    generic map (
         width  => 12
        )
    Port map (
       CE   =>  '1'  ,
       CLK  =>  TOB_TXOUTCLK ,
       RST  =>  TOB_FIFO_sw_rst_i , -- RST OR TOB_FIFO_sw_rst
       UP   =>  frame_cntr_en_ii ,
       DOWN =>  frame_cntr_dec_en_i ,   -- this is a 280 MHz signal
       Q    =>  frame_count_i
       );
 
-- delay data to SPY RAM
U10_dec_frm_cntr : process (TOB_TXOUTCLK)
    begin
        if TOB_TXOUTCLK'event and TOB_TXOUTCLK = '1' then
            TOB_out_to_MGT_1dly             <= TOB_out_to_MGT_i;
            TOB_data_out_MGT_i              <= TOB_out_to_MGT_1dly;        -- data to MGT
            TOB_out_to_MGT_is_char_1dly     <= TOB_out_to_MGT_is_char_i;
            TOB_out_char_MGT_i              <= TOB_out_to_MGT_is_char_1dly;
            T_TOB_out_valid_1dly            <= T_TOB_out_valid_i;
        end if;
    end process;
 
    SPY_TOB_mem_wr_addr_en_i <= (T_TOB_out_valid_1dly AND enable_tob_spy_mem_wr);
 
-- The TOB_SPY_mem is a Dual Port Memory with IPBus interface.
-- It is possible to read/write to/from DPRAM using the IPBus interface.
-- The SPY Memory captures the data that is read out of Link Output FIFO to MGT.
-- The SPY Memory is designed to fill up and then stops accepting new data,
-- therefore the old data is not written over.
 
U12_TOB_SPY_mem : entity ipbus_lib.ipbus_dpram
    generic map(
        ADDR_WIDTH => 11      -- DPRAM 512 locations
    )
    port map(
        clk     => ipb_clk,
        rst     => RST_spy_mem_wr_addr OR RST_i  ,  -- was '0'  ,
        ipb_in  => ipbus_in_tob_dpram ,    -- i/p signal going to TOB SPY DPRAM
        ipb_out => ipbus_out_tob_dpram ,    -- o/p signal coming from TOB SPY DPRAM
        rclk    => TOB_TXOUTCLK ,
        we      => SPY_TOB_mem_wr_addr_en_i ,   -- wr addr en
        d       => TOB_out_to_MGT_1dly ,     -- wr data
        q       => q1_int ,
        addr    => SPY_TOB_mem_wr_addr_i     -- wr addr
    );
 
-- The spy_mem_wr_addr is a generic counter that provides the write address to RAW SPY Memory.
-- The spy memory address is 11-bits wide, so the depth of memory is 2048.
-- The write address of the TOB_SPY_mem is reset to ZERO by asserting RST_spy_mem_wr_addr or system RST signals.
-- The signal RST_spy_mem_wr_addr is bit 5 of register rdout_pulse_reg.
-- The rdout_pulse_reg register is pulsed, and after 1 clock cycle all bits are reset to Zeros.
 
U13_spy_mem_wr_addr : entity TOB_rdout_lib.cntr_generic
    generic map (
         width  => 11
        )
    Port map (
       CE   =>  SPY_TOB_mem_wr_addr_en_i  ,  -- if a valid data, then increment the address
       CLK  =>  TOB_TXOUTCLK ,
       RST  =>  RST_spy_mem_wr_addr OR RST_i  ,
       Q    =>  SPY_TOB_mem_wr_addr_i
       );
 
-- Process U14_stop_wr disables the write enable signal to Spy Memory when it is full.
 
U14_stop_tob_wr : process (TOB_TXOUTCLK)
  begin
    if rising_edge (TOB_TXOUTCLK) then
      if (RST_spy_mem_wr_addr = '1') then
        enable_tob_spy_mem_wr <= '1';   -- if not full, en data wr
      else
        if SPY_TOB_mem_wr_addr_i = "11111111111" then  -- if terminal count -1 to prevent wrap round to ZERO
          enable_tob_spy_mem_wr <= '0';  -- disable memory wr to prevent data corruption
        end if;
      end if;
    end if;
  end process U14_stop_tob_wr;
 
--U14_stop_tob_wr : entity TOB_rdout_lib.fsm_TOB_double_word
--    Port map (
--       CLK_IN  =>  TOB_TXOUTCLK ,
--       RST_IN  =>  RST_spy_mem_wr_addr OR RST_i,
--       TOB_data_in       => TOB_out_to_MGT_1dly,
--       double_counter_en => tob_double_word_en, -- enable TOB double word counter
--       DPR_wr_enable     => enable_tob_spy_mem_wr
--       );
 
end RTL;