fsm_TOBs_to_muxPISO Entity Reference

FSM to write Merged TOBs and Local XTOBs (tau & e/g) data to Link Output FIFO for process FPGA 1 and 2. More...

Inheritance diagram for fsm_TOBs_to_muxPISO:

Entities
Behavioral	architecture
	FSM to write Merged TOBs and Local XTOBs (tau & e/g) data to Link Output FIFO for process FPGA 1 and 2. More...

Libraries
IEEE
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>

Generics
FPGA_NUMBER	integer := 1
	Integer used to distinguish different FPGAs having a slightly different firmware.

Ports
TOB_FIFO_sw_rst	in	std_logic
		TOB Readout FIFO reset Pulse by software command ORed with SYS_RST.
hw_addr	in	STD_LOGIC_VECTOR ( 1 downto 0 )
		FPGA Hardware Address.
trigger_slice_in	in	STD_LOGIC_VECTOR ( 3 downto 0 )
		Trigger slice number - on L1A.
rdout_T_TOB_209b_in	in	STD_LOGIC_VECTOR ( 208 downto 0 )
		sorted TOBs 209b = 7b+4b+6b+192b TOB_BCN+ERR+valid+TOBs
valid_T_TOB_in	in	std_logic
		sorted TOBs valid signal
TOB_type_in	in	STD_LOGIC
		Sorted TOB data readout 32b * 7 in series, only 6 is used - F1 reads e/g TOBs and F2 reads tau TOBs.
XTOBs_eg_in	in	array_8_of_252b
		XTOBs e/g {array 8 of [(5*64b) + 5b valid]}.
valid_XTOBs_eg_in	in	STD_LOGIC
		XTOBs e/g valid signal.
XTOBs_tau_in	in	array_8_of_252b
		XTOBs tau {array 8 of [(5*64b) + 5b valid]}.
valid_XTOBs_tau_in	in	STD_LOGIC
		XTOBs tau valid signal.
clk_280M_in	in	STD_LOGIC
		280MHz clock input signal
shelf_number	in	STD_LOGIC_VECTOR ( 3 downto 0 )
		shelf number input
efex_slot_num	in	STD_LOGIC_VECTOR ( 3 downto 0 )
		eFEX slot number input
TOB_FIFO_empty_in	in	std_logic
		Input empty flag of all TOB FIFOs TTC, TOB & XTOB FIFOs.
TOB_prog_full_flag_in	in	std_logic
		Input prog Full flag of all TOB FIFOs TTC, TOB & XTOB FIFOs.
DPR_locations_to_rd	in	STD_LOGIC_VECTOR ( 2 downto 0 )
		number of DRPAM locations to read for multi-slice (1 to 5)
read_on_err_in	in	STD_LOGIC
		Read RAW data on error flag.
FIFO_BCN_in	in	STD_LOGIC_VECTOR ( 11 downto 0 )
		Bunch Crossing ID from BCN counter.
FIFO_L1A_ID	in	STD_LOGIC_VECTOR ( 23 downto 0 )
		L1A ID from TTC input.
FIFO_L1A_ID_EXT	in	STD_LOGIC_VECTOR ( 7 downto 0 )
		Extended L1A ID from TTC input.
BCN_FIFO_valid_in	in	STD_LOGIC
		Data from TTC FIFO is valid.
LO_FIFO_prog_full_in	in	std_logic
		Link Output FIFO partial FULL flag to receive RAW calorimeter data.
LO_FIFO_data_count_in	in	STD_LOGIC_VECTOR ( 12 downto 0 )
		Link Output FIFO data count.
frame_cntr_en	out	STD_LOGIC
		enable frame counter to count up by 1
BCN_FIFO_rd_en_out	out	STD_LOGIC
		read enable signal to BCN & L1A_ID FIFOs
BCN_FIFO_prog_full_in	in	STD_LOGIC
		BCN & L1A FIFO prog full flag.
TOB_rdout_fifo_rd_en_out	out	STD_LOGIC
		read enable signal to all TOB/XTOB FIFOs
TOB_out_valid	out	STD_LOGIC
		sorted TOBsXTOBs data valid signal to Link_outpout_FIFO
TOB_out_is_char	out	STD_LOGIC
		sorted TOBsXTOBs data is CHAR signal to Link_outpout_FIFO
TOBs_out	out	STD_LOGIC_VECTOR ( 31 downto 0 )
		sorted TOBsXTOBs 32b data to Link_outpout_FIFO
TOB_safe_mode_out	out	STD_LOGIC
		Safe Mode operation flag for TOB readout.
tob_data_mux_fsm	out	STD_LOGIC_VECTOR ( 7 downto 0 )
		Monitor state machine status register.

Detailed Description

FSM to write Merged TOBs and Local XTOBs (tau & e/g) data to Link Output FIFO for process FPGA 1 and 2.

This module creates a complete TOB/XTOB event together with Header and Trailer and writes the entire event into Link Output FIFO. The Link Output FIFO is then controlled by FIFO_to_MGT_FSM state machine to transfer data to MGT.

This FSM is generated to write TOBs and XTOBS into an event packet for pFPGA 1 and 2, and generated to write only XTOBS into an event packet for pFPGA 3 and 4

Process FPGA 1 construct events with merged e/g TOBs from all 4 Process FPGAs and local XTOBs. Process FPGA 2 construct events with merged tau TOBs from all 4 Process FPGAs and local XTOBs. Process FPGA 3 and 4 only construct events with their local XTOBs.

This FSM also handles Header and Trailer construction.

In order to create full TOB/XTOB event (frame) all parallel data from TOBs and XTOBs de-randomisation FIFOs must be read in turn, In multi-slice readout, all parallel data from TOB and XTOB de-randomisation FIFOs must be read twice or more.

When the occupancy of de-randomisation TOB/XTOB Data FIFO or TTC FIFO reaches its prog FULL occupancy level, a Safe Mode Flag is set which is used to create Safe Mode TOB/XTOB events and empty the TOB/XTOB Data FIFO & TTC FIFO. These Safe Mode events consists of 2 Header words, and one Trailer word. The payload consists of two words, a ZERO word together with a sub-trailer word for the slice. Multi-slice readout contains a number of these double words, equal to the number of slices to be readout.

1. Readout operation for Process FPGAs 1 & 2, create Events which consists of only Valid XTOB/TOBs.
   • TOB & XTOB Event in Normal Operation: Read 1 Slice - Takes 179 ticks of 280MHz clock to create one TOB & XTOB Event with 1 Slice Readout.
   • TOB & XTOB Event in Normal Operation: Read 2 Slice - Takes 352 ticks of 280MHz clock to create one TOB & XTOB Event with 2 Slice Readout.
   • TOB & XTOB Event in Normal Operation: Read 3 Slice - Takes 524 ticks of 280MHz clock to create one TOB & XTOB Event with 3 Slice Readout.
   • TOB & XTOB Event in Normal Operation: Read 4 Slice - Takes 697 ticks of 280MHz clock to create one TOB & XTOB Event with 4 Slice Readout.
   • TOB & XTOB Event in SAFE Mode Operation: Read 1 Slices - Takes 8 ticks of 280MHz clock to create one SAFE Mode TOB & XTOB Event. Read 2 Slices - Takes 12 ticks of 280MHz clock to create one SAFE Mode TOB & XTOB Event. etc.
2. Readout operation for Process FPGAs 3 & 4, create Events which consists of only Valid e/g and tau XTOBs..
   • XTOB Event in Normal Operation: Read 1 Slice - Takes 171 ticks of 280MHz clock to create one XTOB Event with 1 Slice Readout.
   • XTOB Event in Normal Operation: Read 2 Slice - Takes 344 ticks of 280MHz clock to create one XTOB Event with 2 Slice Readout.
   • XTOB Event in Normal Operation: Read 3 Slice - Takes 516 ticks of 280MHz clock to create one XTOB Event with 3 Slice Readout.
   • XTOB Event in Normal Operation: Read 4 Slice - Takes 691 ticks of 280MHz clock to create one XTOB Event with 4 Slice Readout.
   • XTOB Event in SAFE Mode Operation: Read 1 Slice - Takes 8 ticks of 280MHz clock to create one SAFE Mode XTOB Event. Read 2 Slice - Takes 12 ticks of 280MHz clock to create one SAFE Mode XTOB Event.

The output of this FSM is:

• 32-bit data word
• 1-bit data is CHAR
• 1-bit valid which is the write enable to Link Output FIFO

Header Word 1:

• TOBs_out_i(31:24) = TOB BCN
• TOBs_out_i(23:20) = XTOB BCN
• TOBs_out_i(19:8) = Local (internal) BCN
• TOBs_out_i(7:0) = ch_sop = X"3C"

Header Word 2:

• TOBs_out_i(31:24) = Extended L1_ID
• TOBs_out_i(23:0) = Level 1 ID

Trailer Word 1: Slice Trailer

• TOBs_out_i(31) = ZERO
• TOBs_out_i(30) = link_err_flg_in_i
• TOBs_out_i(29:28) = FPGA_mapping
• TOBs_out_i(27) = safe mode
• TOBs_out_i(26:24) = slice number transmitted
• TOBs_out_i(23:18) = XTOB counter tau
• TOBs_out_i(17:12) = XTOB counter e/g
• TOBs_out_i(11:9) = TOB counter
• TOBs_out_i(8) = TOB type in
• TOBs_out_i(7:0) = slice_end = X"5C" (K28.2)

Trailer Word 2: Event Trailer

• TOBs_out_i(31) = safe mode
• TOBs_out_i(30:27) = ZERO
• TOBs_out_i(26:24) = DPR_locations_to_rd (number of slices to read)
• TOBs_out_i(23:20) = trigger slice number
• TOBs_out_i(19:8) = TOB payload counter
• TOBs_out_i(7:0) = ch_eop = X"DC"

CHAR constants are defined in data_type_pkg.vhd

• for reference only
  • constant ch_idle : std_logic_vector(7 downto 0) := X"BC" ; – idle char is K28.5
  • constant ch_sop1 : std_logic_vector(7 downto 0) := X"3C" ; – TOB/XTOB star of packet char is K28.1
  • constant ch_sop2 : std_logic_vector(7 downto 0) := X"7C" ; – CALO DATA star of packet char is K28.3
  • constant ch_eop : std_logic_vector(7 downto 0) := X"DC" ; – end of packet char is K28.6
  • constant slice_end : std_logic_vector(7 downto 0) := X"5C" ; – end of slice char is K28.2

TRIGGER SLICE:

• identifies the slice number on L1A, as a number between 0 to 4
• TOB packet header word gets TOB/XTOB BCN from actual trigger slice TOB/XTOB data, but internal BCN from L1A_TOB FIFO
• L1A_TOB BCN is always the BCN on L1A, and must match TOB/XTOB BCN of Trigger Slice value

Author

Saeed Taghavi

Definition at line 115 of file fsm_TOBs_to_muxPISO.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/fsm_TOBs_to_muxPISO.vhd