fsm_TOBs_to_muxPISO.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
use IEEE.NUMERIC_STD.ALL;
--use ieee.numeric_std_unsigned;
 
library TOB_rdout_lib;
use TOB_rdout_lib.TOB_rdout_ip_pkg.ALL;
use TOB_rdout_lib.data_type_pkg.all;
 
entity fsm_TOBs_to_muxPISO is
    Generic
        (
    FPGA_NUMBER : integer := 1
        ) ;
    Port (
       TOB_FIFO_sw_rst          : in std_logic ;
       hw_addr                    : in STD_LOGIC_VECTOR(1 downto 0) ;
       trigger_slice_in           : in STD_LOGIC_VECTOR(3 downto 0) ;
       rdout_T_TOB_209b_in        : in STD_LOGIC_VECTOR(208 downto 0);
       valid_T_TOB_in             : in std_logic ;
       TOB_type_in                : in STD_LOGIC;
       XTOBs_eg_in                : in array_8_of_252b;  -- XTOBs {array 8 of [(5*48b) + 5b valid] + XTOB_BCN}
       valid_XTOBs_eg_in          : in STD_LOGIC ;
       XTOBs_tau_in               : in array_8_of_252b;  -- XTOBs {array 8 of [(5*48b) + 5b valid] + XTOB_BCN}
       valid_XTOBs_tau_in         : in STD_LOGIC ;
       clk_280M_in                : in STD_LOGIC;
       shelf_number  : in STD_LOGIC_VECTOR (3 downto 0);
       efex_slot_num  : in STD_LOGIC_VECTOR (3 downto 0);
       TOB_FIFO_empty_in          : in std_logic ;
       TOB_prog_full_flag_in      : in std_logic ;
       DPR_locations_to_rd        : in STD_LOGIC_VECTOR (2 downto 0);
       read_on_err_in             : in STD_LOGIC;
       FIFO_BCN_in                : in STD_LOGIC_VECTOR (11 downto 0);
       FIFO_L1A_ID                : in STD_LOGIC_VECTOR (23 downto 0);
       FIFO_L1A_ID_EXT            : in STD_LOGIC_VECTOR (7 downto 0);
       BCN_FIFO_valid_in          : in STD_LOGIC;
       LO_FIFO_prog_full_in        : in  std_logic ;
       LO_FIFO_data_count_in      : in  STD_LOGIC_VECTOR (12 downto 0)  ;
       frame_cntr_en              : out STD_LOGIC;
       BCN_FIFO_rd_en_out         : out STD_LOGIC;
       BCN_FIFO_prog_full_in       : in STD_LOGIC;
       TOB_rdout_fifo_rd_en_out   : out STD_LOGIC;
       TOB_out_valid              : out STD_LOGIC;
       TOB_out_is_char            : out STD_LOGIC;
       TOBs_out                   : out STD_LOGIC_VECTOR (31 downto 0);
       TOB_safe_mode_out          : out STD_LOGIC;
       tob_data_mux_fsm        : out STD_LOGIC_VECTOR (7 downto 0)
   );
 
end fsm_TOBs_to_muxPISO;
 
architecture Behavioral of fsm_TOBs_to_muxPISO is
 
    type FPGA_mapping_array is array(3 downto 0) of std_logic_vector(1 downto 0);
    constant FPGA_mapping               : FPGA_mapping_array := ("10", "01", "11", "00") ; -- HW address to processor number
 
    signal  TOB_out_valid_i              : std_logic;
    signal  TOB_rdout_fifo_rd_en_i       : std_logic ;
    signal  corrective_trailer           : std_logic ;
 
    signal  BCN_FIFO_rd_en_i             : std_logic  ;
    signal  BCN_FIFO_valid_in_i          : std_logic  ;
 
    signal  slice_count_i                : unsigned (2 downto 0):= (others => '0');
    signal  link_err_flg_in_i            : STD_LOGIC_VECTOR(3  downto 0):= (others => '0');
    signal  TOB_BCN_in_i                 : STD_LOGIC_VECTOR(7 downto 0):= (others => '0');
    signal  FIFO_BCN_in_i                : STD_LOGIC_VECTOR(11 downto 0):= (others => '0');
    signal  XTOB_eg_BCN_in_i             : std_logic_vector (7 downto 0):= (others => '0');
    signal  XTOB_hdr_BCN_in_i            : std_logic_vector (7 downto 0):= (others => '0');
    signal  XTOB_tau_BCN_in_i            : std_logic_vector (7 downto 0):= (others => '0');
    signal  FIFO_L1A_ID_i                : STD_LOGIC_VECTOR(23 downto 0):= (others => '0');
    signal  FIFO_L1A_ID_EXT_i            : STD_LOGIC_VECTOR(7  downto 0):= (others => '0');
 
    signal  TOBs_out_i                   : STD_LOGIC_VECTOR(31 downto 0):= (others => '0');
 
    signal  TOB_out_is_char_i      : std_logic ;
    signal  write_in_LO_FIFO_i     : std_logic  ;
 
    signal  CLK_280M_i             : std_logic ;
 
    signal  cntr_rst_i             : std_logic  ;
    signal  TOB_cntr_rst           : std_logic  ;
    signal  T_TOB_cntr_en_i        : std_logic := '0' ;
    signal  T_TOB_cntr_i           : std_logic_vector(3 downto 0) := (others => '0');
    signal  T_TOB_cntr_1dly        : std_logic_vector(3 downto 0) := (others => '0');
 
    signal  XTOB_eg_cntr_en_i      : std_logic := '0' ;
    signal  XTOB_eg_cntr_i         : std_logic_vector(6 downto 0) := (others => '0');
    signal  XTOB_eg_cntr_1dly      : std_logic_vector(6 downto 0) := (others => '0');
    signal  XTOB_tau_cntr_en_i     : std_logic := '0' ;
    signal  XTOB_tau_cntr_i        : std_logic_vector(6 downto 0) := (others => '0');
    signal  XTOB_tau_cntr_1dly     : std_logic_vector(6 downto 0) := (others => '0');
 
    signal  trailer_cntr_en        : std_logic ;
    signal  payld_cntr_rst         : std_logic ;
    signal  payld_cntr_rst_i       : std_logic ;
    signal  payld_cntr_en          : std_logic := '0' ;
    signal  TOB_payld_cntr_i       : std_logic_vector(11 downto 0) := (others => '0');
    signal  TOB_payld_cntr_1dly    : std_logic_vector(11 downto 0) := (others => '0');
 
    signal  frame_cntr_en_i        : std_logic ;
    signal  slice_no_txed          : std_logic_vector(2 downto 0) := (others => '0');  -- slice number transmitted
 
    signal  T_TOB_eg_i           : std_logic_vector(191 downto 0) := (others => '0');
    signal  T_TOB_eg_valid_i     : std_logic_vector(5 downto 0) := (others => '0');
--    signal  FIFO_output_valid_i  : std_logic ;
    signal  valid_XTOBs_eg_i     : std_logic ;
    signal  valid_XTOBs_tau_i    : std_logic ;
 
    signal  XTOB_eg_i            : array_8_of_240b;  -- XTOBs e/g {array 8 of [(5*48b) + 5b valid]};
    signal  XTOB_eg_valid_i      : array_8_of_5b ;  -- std_logic_vector(39 downto 0);
    signal  XTOB_tau_i           : array_8_of_240b;  -- XTOBs tau {array 8 of [(5*48b) + 5b valid]};
    signal  XTOB_tau_valid_i     : array_8_of_5b;   -- std_logic_vector(39 downto 0);
 
    signal  safe_mode_i         : std_logic ;
    signal  miss_sop_i          : std_logic ;   -- signal to miss SOP for multi-slice readout
    signal  wr_en_i             : std_logic ;   -- enable write into link output fifo when not pfull
 
    TYPE STATE_TYPE IS (
       idle, idle_1, wait1, wait2, wait3, wait4, wait5,
       err_sop, err_eop,
       norm_sop1, norm_sop2, norm_tlr, norm_eop,
       rd_fifo, sub_trl_1, sub_trl_2,
       rdout_T_TOB_eg,
       rdout_XTOB_eg_a0, rdout_XTOB_eg_a, rdout_XTOB_eg_b, rdout_XTOB_tau_a0, rdout_XTOB_tau_a, rdout_XTOB_tau_b
       );
 
    SIGNAL current_state : STATE_TYPE;
    signal i            : integer range 0 to 9;       -- used to index TOB valid flag
--    signal j, n         : integer range 0 to 9;       -- used to index TOB valid flag
    signal m_s_count    : integer range 0 to 7;       -- used to count number of multi slice data 1 to 5
 
--    ####### attributes  ########
    attribute keep       : string ;
    attribute max_fanout : integer;
 
--    attribute keep of       i : signal is "true" ;
--    attribute max_fanout of i : signal is 30;
--    attribute keep of       TOBs_out_i : signal is "true" ;
--    attribute max_fanout of TOBs_out_i : signal is 30;
--    attribute keep of       TOB_rdout_fifo_rd_en_i : signal is "true" ;
--    attribute max_fanout of TOB_rdout_fifo_rd_en_i : signal is 30;
--    attribute keep of       TOB_FIFO_sw_rst : signal is "true" ;
--    attribute max_fanout of TOB_FIFO_sw_rst : signal is 30;
--    attribute keep of       write_in_LO_FIFO_i : signal is "true" ;
--    attribute max_fanout of write_in_LO_FIFO_i : signal is 30;
--    attribute keep of       wr_en_i : signal is "true" ;
--    attribute max_fanout of wr_en_i : signal is 30;
--    attribute keep of       TOB_FIFO_empty_in : signal is "true" ;
--    attribute max_fanout of TOB_FIFO_empty_in : signal is 30;
--    attribute keep of       LO_FIFO_prog_full_in : signal is "true" ;
--    attribute max_fanout of LO_FIFO_prog_full_in : signal is 30;
--    attribute keep of       TOB_prog_full_flag_in : signal is "true" ;
--    attribute max_fanout of TOB_prog_full_flag_in : signal is 30;
--    attribute keep of       valid_XTOBs_eg_i : signal is "true" ;
--    attribute max_fanout of valid_XTOBs_eg_i : signal is 30;
--    #######################################
 
begin
 
    -- input ports
    corrective_trailer   <= '0';    -- set corrective_trailer to ZERO
    CLK_280M_i           <= CLK_280M_in ;
 
    -- output ports
    frame_cntr_en             <= frame_cntr_en_i ;
    BCN_FIFO_rd_en_out        <= BCN_FIFO_rd_en_i ;
 
    TOB_safe_mode_out <= safe_mode_i;
 
-- clk data input to remove timing error
U1_clk_280_proc : Process (CLK_280M_i)
    begin
        if rising_edge (CLK_280M_i) then
 
--            FIFO_output_valid_i <= valid_T_TOB_in OR valid_XTOBs_eg_in OR valid_XTOBs_tau_in;
            valid_XTOBs_eg_i <= valid_XTOBs_eg_in;
 
            -- output ports
            TOBs_out             <= TOBs_out_i ;
            TOB_out_valid        <= TOB_out_valid_i ;
            TOB_out_is_char      <= TOB_out_is_char_i ;
            TOB_rdout_fifo_rd_en_out  <= TOB_rdout_fifo_rd_en_i  ;
            -- input signals
            FIFO_BCN_in_i        <= FIFO_BCN_in ;   -- 12b BCN ID from FIFO
            FIFO_L1A_ID_i        <= FIFO_L1A_ID ;   -- 24b L1A ID from FIFO
            FIFO_L1A_ID_EXT_i    <= FIFO_L1A_ID_EXT ;   -- 8b L1A ID Extended from FIFO
            BCN_FIFO_valid_in_i  <= BCN_FIFO_valid_in ;   -- TTC FIFO output is valid
 
            T_TOB_eg_i           <= rdout_T_TOB_209b_in(191 downto 0) ;     -- 6*32=192b TOB data
            T_TOB_eg_valid_i     <= rdout_T_TOB_209b_in(197 downto 192) ;   -- 6b  Valid flags
            link_err_flg_in_i    <= rdout_T_TOB_209b_in(201 downto 198) ;   -- 4 b Error
            TOB_BCN_in_i         <= std_logic_vector( unsigned('0' & rdout_T_TOB_209b_in(208 downto 202))
                                                    + unsigned(trigger_slice_in) );   -- 7b TOB_BCN + trigger_slice_no
 
            T_TOB_cntr_1dly     <= T_TOB_cntr_i ;
            XTOB_eg_cntr_1dly   <= XTOB_eg_cntr_i ;
            XTOB_tau_cntr_1dly  <= XTOB_tau_cntr_i ;
            TOB_payld_cntr_1dly <= TOB_payld_cntr_i ;
        end if;
    end process;
 
    TOB_cntr_rst <= cntr_rst_i OR TOB_FIFO_sw_rst;    -- sw rst already includes RST
 
-- T_TOB_cntr counter, counts the total number of Valid Sorted TOBs.
U2_T_TOB_cntr : entity TOB_rdout_lib.cntr_generic
    generic map(
        width  =>  4
        )
    Port map (
       CE   =>  T_TOB_cntr_en_i ,
       CLK  =>  CLK_280M_i ,
       RST  =>  TOB_cntr_rst,
       Q    =>  T_TOB_cntr_i     -- count every valid T_TOB e/g
       );
 
-- XTOB_eg_cntr counter, counts the total number of valid e/g XTOBs.
U2_XTOB_eg_cntr : entity TOB_rdout_lib.cntr_generic
    generic map(
        width  =>  7
        )
    Port map (
       CE   =>  XTOB_eg_cntr_en_i ,
       CLK  =>  CLK_280M_i ,
       RST  =>  TOB_cntr_rst,
       Q    =>  XTOB_eg_cntr_i      -- count every valid XTOB e/g
       );
 
-- XTOB_tau_cntr counter, counts the total number of valid tau XTOBs.
U2_XTOB_tau_cntr : entity TOB_rdout_lib.cntr_generic
    generic map(
        width  =>  7
        )
    Port map (
       CE   =>  XTOB_tau_cntr_en_i ,
       CLK  =>  CLK_280M_i ,
       RST  =>  TOB_cntr_rst,
       Q    =>  XTOB_tau_cntr_i     -- count every valid XTOB tau
       );
 
    payld_cntr_rst <= payld_cntr_rst_i OR TOB_FIFO_sw_rst;  -- sw rst already includes RST
    payld_cntr_en  <= T_TOB_cntr_en_i OR XTOB_eg_cntr_en_i OR XTOB_tau_cntr_en_i OR trailer_cntr_en;
 
 
-- TOB_payld_length counter, counts the total number of payload data inserted between the Header and Trailer of a TOB/XTOB Event.
U2_TOB_payld_length : entity TOB_rdout_lib.cntr_generic
    generic map(
        width  =>  12
        )
    Port map (
       CE   =>  payld_cntr_en ,     -- count every valid data word (32b words)
       CLK  =>  CLK_280M_i ,
       RST  =>  payld_cntr_rst,
       Q    =>  TOB_payld_cntr_i     -- count every valid data word
       );
 
-- This process disables writing to Link Output FIFO when the LO_FULL reaches a specific occupancy level of 0X1FF0.
U3A_proc1 : process (CLK_280M_i)
begin
    if rising_edge (CLK_280M_i) then
       if (unsigned(LO_FIFO_data_count_in) < X"1FF0") then  -- 8128 leaves enough space for a Safe Mode event
           -- if LO_FIFO is nearly FULL then stop reading from de-randomistion FIFO
           write_in_LO_FIFO_i <= '1';
       else
           write_in_LO_FIFO_i <= '0' ;
       end if;
    end if;
  end process;
 
-- select tau or e/g Topo TOB the counter is counting
    -- FPGA F1 counting Topo TOB e/g
    -- FPGA F2 counting Topo TOB tau
    -- FPGA F3 & 4 NOT counting Topo TOBs = ZERO
 
     wr_en_i <= write_in_LO_FIFO_i ;    -- enable write into link output fifo when not pfull
 
U4_rd_fsm : process (CLK_280M_i)
    variable k, j  : integer range 0 to 10 ;       -- used to index TOB valid flag
 
begin
    if CLK_280M_i'event and CLK_280M_i = '1' then
        if ( TOB_FIFO_sw_rst = '1' )then        -- signal is RST OR TOB_FIFO_sw_rst
            current_state           <= idle ;
            safe_mode_i             <= '0' ;
            cntr_rst_i              <= '1' ;    -- force a reset
            payld_cntr_rst_i        <= '1' ;    -- force a reset
            T_TOB_cntr_en_i         <= '0' ;
            XTOB_eg_cntr_en_i       <= '0' ;
            XTOB_tau_cntr_en_i      <= '0' ;
            TOBs_out_i              <= (others => '0') ;
            tob_data_mux_fsm        <= X"00";
        else
            CASE current_state is
                when idle =>
                    tob_data_mux_fsm     <= X"01";
                    slice_count_i        <= unsigned (DPR_locations_to_rd) ; -- multi-slice read register 1 to 5
                    miss_sop_i                <= '0' ;    -- do not miss SOP
                    cntr_rst_i                <= '0' ;
                    payld_cntr_rst_i          <= '0' ;
                    frame_cntr_en_i           <= '0' ;
                    trailer_cntr_en           <= '0' ;
                    BCN_FIFO_rd_en_i          <= '0' ;
                    TOB_rdout_fifo_rd_en_i    <= '0' ;
                    T_TOB_cntr_en_i           <= '0' ;
                    XTOB_eg_cntr_en_i         <= '0' ;
                    XTOB_tau_cntr_en_i        <= '0' ;
                    TOB_out_valid_i           <= '0' ;
                    TOB_out_is_char_i         <= '0' ;
                    m_s_count                 <=  0 ;
                    i  <= 0 ;
                    j  := 0 ;
                    k  := 0 ;
                    slice_no_txed             <= "000";  -- initially set to 1
                    if (write_in_LO_FIFO_i = '1' )  then -- if LO_FIFO is not full, less than X"1FF0"
                        if (TOB_FIFO_empty_in = '0') then   -- if TOB/XTOB FIFOs are not empty
                            current_state        <= idle_1 ;
                        else
                            current_state        <= idle ;
                        end if;
                    end if;
 
                when idle_1 =>       -- wait 1 clk for fifo empty output
                    tob_data_mux_fsm     <= X"02";
                    if (TOB_FIFO_empty_in = '0') then   -- if TOB FIFOs are not empty
                        -- if LO_FIFO is partial FULL AND TOB_FIFO_prog_full NOT set, then pause
                        if (LO_FIFO_prog_full_in = '1' AND TOB_prog_full_flag_in = '0')  then
                            current_state        <= idle_1 ;
                        else
                            TOB_rdout_fifo_rd_en_i  <= '1';   -- read data from fifos
                            BCN_FIFO_rd_en_i      <= '1' ;    -- read data from BCN fifo
                            current_state        <= wait5 ;
                        end if;
                    else
                        current_state        <= idle ;
                    end if;
 
                when wait5 =>       -- wait 1 clk for fifo output
                    tob_data_mux_fsm    <= X"03";
                    trailer_cntr_en     <= '0' ;
                    cntr_rst_i          <= '0' ;
                    TOB_out_is_char_i   <= '0';
                    TOB_out_valid_i     <= '0' ;
                    BCN_FIFO_rd_en_i    <= '0' ;    -- read data from BCN fifo
                    TOB_rdout_fifo_rd_en_i  <= '0';   -- read data from fifos
 
                -- if BCN_L1A FIFO is partial FULL, then SAFE MODE, empty FIFOs
                    if (BCN_FIFO_prog_full_in = '1')  then
                        safe_mode_i           <= '1' ;    -- enable safe mode flag
--                        TOB_rdout_fifo_rd_en_i  <= '0';   -- read data from fifos
                       current_state      <=  norm_sop1   ;
                    else    -- read data
--                        TOB_rdout_fifo_rd_en_i  <= '0';   -- read data from fifos
                        safe_mode_i             <= '0' ;  -- disable safe mode flag
                        current_state       <=  rd_fifo   ;
                    end if;
 
                when rd_fifo =>       -- wait 1 clk for fifo output
                    tob_data_mux_fsm    <= X"04";
--                  Use eg XTOB BCN for header, correcting for trigger slice offset
                    XTOB_hdr_BCN_in_i      <= std_logic_vector( unsigned ('0' & XTOBs_eg_in(0)(251 downto 245))
                                                              + unsigned (trigger_slice_in) );
 
                    XTOB_eg_i(0)           <= XTOBs_eg_in(0)(239 downto 0); -- XTOBs {array 8 of [(5*48b)
                    XTOB_eg_i(1)           <= XTOBs_eg_in(1)(239 downto 0);
                    XTOB_eg_i(2)           <= XTOBs_eg_in(2)(239 downto 0);
                    XTOB_eg_i(3)           <= XTOBs_eg_in(3)(239 downto 0);
                    XTOB_eg_i(4)           <= XTOBs_eg_in(4)(239 downto 0);
                    XTOB_eg_i(5)           <= XTOBs_eg_in(5)(239 downto 0);
                    XTOB_eg_i(6)           <= XTOBs_eg_in(6)(239 downto 0);
                    XTOB_eg_i(7)           <= XTOBs_eg_in(7)(239 downto 0);
 
                    XTOB_eg_valid_i(0)     <= XTOBs_eg_in(0)(244 downto 240);
                    XTOB_eg_valid_i(1)     <= XTOBs_eg_in(1)(244 downto 240);
                    XTOB_eg_valid_i(2)     <= XTOBs_eg_in(2)(244 downto 240);
                    XTOB_eg_valid_i(3)     <= XTOBs_eg_in(3)(244 downto 240);
                    XTOB_eg_valid_i(4)     <= XTOBs_eg_in(4)(244 downto 240);
                    XTOB_eg_valid_i(5)     <= XTOBs_eg_in(5)(244 downto 240);
                    XTOB_eg_valid_i(6)     <= XTOBs_eg_in(6)(244 downto 240);
                    XTOB_eg_valid_i(7)     <= XTOBs_eg_in(7)(244 downto 240);
 
                    XTOB_eg_BCN_in_i       <= '0' & XTOBs_eg_in(0)(251 downto 245);
 
                    XTOB_tau_i(0)           <= XTOBs_tau_in(0)(239 downto 0);   -- XTOBs {array 8 of [(5*34b)
                    XTOB_tau_i(1)           <= XTOBs_tau_in(1)(239 downto 0);
                    XTOB_tau_i(2)           <= XTOBs_tau_in(2)(239 downto 0);
                    XTOB_tau_i(3)           <= XTOBs_tau_in(3)(239 downto 0);
                    XTOB_tau_i(4)           <= XTOBs_tau_in(4)(239 downto 0);
                    XTOB_tau_i(5)           <= XTOBs_tau_in(5)(239 downto 0);
                    XTOB_tau_i(6)           <= XTOBs_tau_in(6)(239 downto 0);
                    XTOB_tau_i(7)           <= XTOBs_tau_in(7)(239 downto 0);
 
                    XTOB_tau_valid_i(0)     <= XTOBs_tau_in(0)(244 downto 240);
                    XTOB_tau_valid_i(1)     <= XTOBs_tau_in(1)(244 downto 240);
                    XTOB_tau_valid_i(2)     <= XTOBs_tau_in(2)(244 downto 240);
                    XTOB_tau_valid_i(3)     <= XTOBs_tau_in(3)(244 downto 240);
                    XTOB_tau_valid_i(4)     <= XTOBs_tau_in(4)(244 downto 240);
                    XTOB_tau_valid_i(5)     <= XTOBs_tau_in(5)(244 downto 240);
                    XTOB_tau_valid_i(6)     <= XTOBs_tau_in(6)(244 downto 240);
                    XTOB_tau_valid_i(7)     <= XTOBs_tau_in(7)(244 downto 240);
 
                    XTOB_tau_BCN_in_i       <= '0' & XTOBs_tau_in(0)(251 downto 245);
 
                    trailer_cntr_en     <= '0' ; -- stop counter counting coming here from sub_tlr_2
                    TOB_rdout_fifo_rd_en_i    <= '0' ;
                    TOB_out_valid_i           <= '0' ;      -- do not save in FIFO
                    if valid_XTOBs_eg_i = '1' then -- if TOBs/XTOBs are valid, write to LO FIFO -- works for all pFPGAs
                        if miss_sop_i = '0'  then     -- insert SOP
                            current_state   <= norm_sop1 ;
                        else                         -- miss SOP
                            current_state   <= rdout_T_TOB_eg ;
                        end if;
                    else    -- if no valid TOBs yet, wait
                      current_state   <= rd_fifo ;  -- stay until FIFO read
                    end if;
 
                when norm_sop1 =>            -- normal data header SOP 1
                    tob_data_mux_fsm    <= X"05";
                    -- readout expected + 11b reserved + BCN  & K28.1
                    TOB_rdout_fifo_rd_en_i  <= '0' ;
                    -- work out trigger slice number by subtracting TOB BCN from internal BCN
                    TOBs_out_i              <= "0" & TOB_BCN_in_i(6 downto 0) & XTOB_hdr_BCN_in_i(3 downto 0) & FIFO_BCN_in_i & ch_sop1 ;
                    TOB_out_is_char_i       <= '1';
                    TOB_out_valid_i         <= '1' ;      -- save in FIFO
                    current_state           <= norm_sop2 ;
 
                when norm_sop2 =>            -- normal data header SOP 2
                    tob_data_mux_fsm    <= X"06";
                    TOBs_out_i              <= FIFO_L1A_ID_EXT_i & FIFO_L1A_ID_i ;  -- L1A_ID_EXT + L1A ID
                    TOB_out_is_char_i       <= '0';
                    TOB_out_valid_i         <= '1' ;
                    if ( safe_mode_i = '1' ) then  -- if in SAFE MODE or Read on Error mode
                        current_state         <= sub_trl_1 ;
                    else    -- normal read operation
                        current_state         <= rdout_T_TOB_eg ;
                    end if;
 
                when rdout_T_TOB_eg =>         -- normal T_TOB_eg rd out 7 clks
                    tob_data_mux_fsm    <= X"07";
                    TOB_out_is_char_i     <= '0';
                    T_TOB_cntr_en_i       <= T_TOB_eg_valid_i(i) AND wr_en_i;
                    TOBs_out_i            <= T_TOB_eg_i((((i*32)+32)-1) downto (i*32));
                    TOB_out_valid_i       <= T_TOB_eg_valid_i(i) AND wr_en_i;    -- on valid save in FIFO
                     if (i = 5) then        -- 6 T TOBs are read out, 7th is ignored
                       i <= 0;
                       current_state   <= rdout_XTOB_eg_a0;
                    else
                       current_state   <= rdout_T_TOB_eg ;
                       i <= i + 1 ;
                    end if;
 
-- XTOBs e/g array 8 of [(5*64b)
-- j = 0  and k = 0
                when rdout_XTOB_eg_a0 =>         -- normal X_TOB_eg rd out 80 clks
                    j := 0;
                    k := 0;
                    tob_data_mux_fsm    <= X"08";
                    T_TOB_cntr_en_i     <= '0';    -- to prevent a 1 on last data to persist
                    XTOB_eg_cntr_en_i   <= XTOB_eg_valid_i(j)(k) AND wr_en_i;
                    TOB_out_valid_i     <= XTOB_eg_valid_i(j)(k) AND wr_en_i;    -- on valid save in FIFO
                    TOBs_out_i          <= XTOB_eg_i(j)(31 downto 0);
                    current_state       <= rdout_XTOB_eg_b ;
 
                when rdout_XTOB_eg_a =>         -- normal X_TOB_eg rd out 80 clks
                    XTOB_eg_cntr_en_i   <= XTOB_eg_valid_i(j)(k) AND wr_en_i;
                    TOB_out_valid_i     <= XTOB_eg_valid_i(j)(k) AND wr_en_i;    -- on valid save in FIFO
                    TOBs_out_i          <= XTOB_eg_i(j)(31 downto 0);
                    current_state       <= rdout_XTOB_eg_b ;
 
                when rdout_XTOB_eg_b =>         -- normal X_TOB_eg rd out 80 clks
                    XTOB_eg_cntr_en_i   <= XTOB_eg_valid_i(j)(k) AND wr_en_i;
                    TOB_out_valid_i     <= XTOB_eg_valid_i(j)(k) AND wr_en_i;    -- on valid save in FIFO
                    TOBs_out_i          <= XTOB_eg_BCN_in_i(3 downto 0) & shelf_number & efex_slot_num & "0000" & XTOB_eg_i(j)(47 downto 32);
                    XTOB_eg_i(j)        <= X"000000000000" & XTOB_eg_i(j)(239 downto 48);
-- iterate over j 0 - 7, k 0 - 4
                    if (k = 4) then
                       if (j = 7) then
                          current_state       <= rdout_XTOB_tau_a0;
                       else
                          j := j + 1;
                          k := 0;
                          current_state       <= rdout_XTOB_eg_a;
                       end if;
                    else
                       k := k + 1;
                       current_state       <= rdout_XTOB_eg_a;
                    end if;
 
-- XTOBs tau array 8 of (5*64b)
-- j = 0  and k = 0
                when rdout_XTOB_tau_a0 =>         -- normal X_TOB_eg rd out 80 clks
                    tob_data_mux_fsm    <= X"09";
                    k := 0;
                    j := 0;
                    XTOB_eg_cntr_en_i <= '0' ;    -- to prevent a 1 on last data to persist
                    XTOB_tau_cntr_en_i  <= XTOB_tau_valid_i(j)(k) AND wr_en_i;
                    TOB_out_valid_i     <= XTOB_tau_valid_i(j)(k) AND wr_en_i;    -- on valid save in FIFO
                    TOBs_out_i          <= XTOB_tau_i(j)(31 downto 0);
                    current_state        <= rdout_XTOB_tau_b ;
 
                when rdout_XTOB_tau_a =>         -- normal X_TOB_eg rd out 80 clks
                    XTOB_tau_cntr_en_i  <= XTOB_tau_valid_i(j)(k) AND wr_en_i;
                    TOB_out_valid_i     <= XTOB_tau_valid_i(j)(k) AND wr_en_i;    -- on valid save in FIFO
                    TOBs_out_i          <= XTOB_tau_i(j)(31 downto 0);
                    current_state        <= rdout_XTOB_tau_b ;
 
                when rdout_XTOB_tau_b =>         -- normal X_TOB_eg rd out 80 clks
                    XTOB_tau_cntr_en_i  <= XTOB_tau_valid_i(j)(k) AND wr_en_i;
                    TOB_out_valid_i     <= XTOB_tau_valid_i(j)(k) AND wr_en_i;    -- on valid save in FIFO
                    TOBs_out_i          <= XTOB_tau_BCN_in_i(3 downto 0) & shelf_number & efex_slot_num & "0000" & XTOB_tau_i(j)(47 downto 32);
                    XTOB_tau_i(j)        <= X"000000000000" & XTOB_tau_i(j)(239 downto 48);
-- iterate over j 0 - 7, k 0 - 4
                    if (k = 4) then
                       if (j = 7) then
                          current_state       <= wait1;
                       else
                          j := j + 1;
                          k := 0;
                          current_state       <= rdout_XTOB_tau_a;
                       end if;
                    else
                       k := k + 1;
                       current_state       <= rdout_XTOB_tau_a;
                    end if;
 
                when wait1 =>       -- wait for delayed counter to be valid in sub_trl_1
                    tob_data_mux_fsm    <= X"0A";
                    XTOB_tau_cntr_en_i  <= '0' ;    -- to prevent a 1 on last data to persist
                    TOB_out_valid_i     <= '0' ;    -- do not save in FIFO
--                        TOBs_out_i          <=  X"00000000" ;
                    current_state       <= sub_trl_1;   -- wait2 ;   -- wait for counter to count up.
 
                when wait2 =>       -- wait for delayed counter to be valid in sub_trl_1
                    tob_data_mux_fsm    <= X"0B";
                    trailer_cntr_en     <= '0' ;
                    TOB_out_is_char_i   <= '0';
                    TOB_out_valid_i     <= '0' ;
                    current_state       <= sub_trl_1 ;   -- wait for counter to count up.
 
                when sub_trl_1 =>            -- ZERO data trailer
                    tob_data_mux_fsm    <= X"0C";
                    trailer_cntr_en     <= '0' ;
                    cntr_rst_i          <= '0' ;
                    TOB_rdout_fifo_rd_en_i  <= '0';         -- stop read from FIFO
                    slice_no_txed         <= std_logic_vector(to_unsigned(m_s_count,3));  --  1st slice is ZERO
                    m_s_count             <= m_s_count + 1 ;      -- increment multi slice readout count
                    TOB_out_valid_i       <= '0' ;    -- do not save in FIFO
                    TOB_out_is_char_i     <= '0';
                    if TOB_payld_cntr_i(0) = '0' OR safe_mode_i = '1' then       -- no. of 32b words even so send a ZERO word
                        TOB_out_valid_i         <= '1' ;
                        TOBs_out_i              <=  X"00000000" ;
                        trailer_cntr_en         <= '1' ;    -- increment the payload counter to count the ZERO word
                    end if;
                    current_state           <= sub_trl_2 ;
 
                when sub_trl_2 =>            -- normal data trailer
                    tob_data_mux_fsm    <= X"0D";
                    trailer_cntr_en         <= '1' ;    -- increment the payload counter to count the trailer.
                    -- no. of 32b words is odd so just send trailer which makes even
                    TOB_out_is_char_i       <= '1';
                    TOB_out_valid_i         <= '1' ;
                    -- 1b err_rd + 7b 0 + 2b FPGA no + 1b TSM + 3b Slice + 6b 64b Tau XTOB  + 6b 64b e/g XTOB + 3b 32b TOB cntr + 1b TOB type
                    TOBs_out_i              <=  '0' & read_on_err_in & FPGA_mapping(to_integer(unsigned(hw_addr))) & safe_mode_i & slice_no_txed &
                                                XTOB_tau_cntr_1dly(6 downto 1) & XTOB_eg_cntr_1dly(6 downto 1) & T_TOB_cntr_1dly(2 downto 0) &
                                                TOB_type_in & slice_end;    -- slice_end = X"5C"
                    i <= 0 ;
                    if m_s_count = slice_count_i then
                        current_state           <= wait3 ;
                    else    -- if not in Safe Mode, normal read
                        cntr_rst_i              <= '1' ;    -- reset the TOB counters
                        if safe_mode_i = '0' then
                            miss_sop_i              <= '1' ;        -- miss SOP for multi-slice readout
                            TOB_rdout_fifo_rd_en_i  <= '1';         -- read next slice from FIFO
                            current_state           <= wait5 ;      -- was idle (just in case fifo is empty ie lost sync with data in
                        else    -- if in Safe Mode, empty buffers
                            miss_sop_i              <= '1' ;        -- miss SOP for multi-slice readout
                            TOB_rdout_fifo_rd_en_i  <= '1';         -- read next slice from FIFO
                            current_state           <= wait2 ;  -- empty next slice in Safe Mode, but allow payload counter to count up
                        end if;
                    end if;
 
                when wait3 =>
                    tob_data_mux_fsm    <= X"0E";
                    trailer_cntr_en     <= '0' ;
                    m_s_count           <=  0 ;
                    TOB_out_is_char_i   <= '0';
                    TOB_out_valid_i     <= '0' ;
                    current_state       <= wait4 ;   -- wait for counter to count up.
 
                when wait4 =>
                    TOB_out_valid_i     <= '0' ;
                    current_state       <= norm_eop ;   -- extra delay to remove timing error.
 
                when norm_eop =>        -- normal end of packet
                    frame_cntr_en_i     <= '1' ;    -- inclrease frame counter by 1
                    payld_cntr_rst_i    <= '1' ;    -- reset the pay loadcounters
                    cntr_rst_i          <= '1' ;    -- reset the TOB counters
                    TOB_out_is_char_i   <= '1';
                    TOBs_out_i          <= safe_mode_i & "0000" & DPR_locations_to_rd & trigger_slice_in & TOB_payld_cntr_1dly(11 downto 0) & ch_eop ; -- pay load cntr is divided by 2 to show number of 32b owrds
                    TOB_out_valid_i     <= '1' ;
                    current_state       <= idle ;
 
                when others =>
                    NULL;
            end case;
        end if;
    END IF;
end process;
 
 
--U2_ila_TOB_XTOB_in : ila_ipbus_fabric_rd_wr
--PORT MAP (
--  clk    =>  CLK_280M_i,
--  probe0(3 downto 0)    =>  T_TOB_cntr_i ,       -- 36b
--  probe0(4)             =>  T_TOB_cntr_en_i ,       -- 36b
--  probe0(11 downto 5)   =>  XTOB_eg_cntr_i ,       -- 36b
--  probe0(12)            =>  XTOB_eg_cntr_en_i,       -- 36b
--  probe0(19 downto 13)  =>  XTOB_tau_cntr_i ,       -- 36b
--  probe0(20)            =>  XTOB_tau_cntr_en_i,       -- 36b
--  probe0(32 downto 21)  =>  TOB_payld_cntr_1dly ,       -- 36b
--  probe0(35 downto 33)  =>  (others => '0') ,       -- 36b
--  probe1(5 downto 0)    =>  T_TOB_eg_valid_i,  -- 36b
--  probe1(10 downto 6)    =>  XTOB_eg_valid_i(0),  -- 36b
--  probe1(15 downto 11)   =>  XTOB_eg_valid_i(1),  -- 36b
--  probe1(20 downto 16)   =>  XTOB_eg_valid_i(2),  -- 36b
--  probe1(25 downto 21)   =>  XTOB_eg_valid_i(3),  -- 36b
--  probe1(30 downto 26)   =>  XTOB_eg_valid_i(4),  -- 36b
--  probe1(35 downto 31)   =>  XTOB_eg_valid_i(5),  -- 36b
--  probe2(0) =>  cntr_rst_i ,   -- 1b
--  probe3(0) =>  payld_cntr_rst_i ,           -- 1b
--  probe4(0) =>  TOB_FIFO_sw_rst ,   -- 1b
--  probe5(0) =>  '0',  -- 36b
--  probe5(5 downto 1)     =>  XTOB_tau_valid_i(0),  -- 36b
--  probe5(10 downto 6)    =>  XTOB_tau_valid_i(1),  -- 36b
--  probe5(15 downto 11)   =>  XTOB_tau_valid_i(2),  -- 36b
--  probe5(20 downto 16)   =>  XTOB_tau_valid_i(3),  -- 36b
--  probe5(25 downto 21)   =>  XTOB_tau_valid_i(4),  -- 36b
--  probe5(30 downto 26)   =>  XTOB_tau_valid_i(5),  -- 36b
--  probe5(35 downto 31)   =>  XTOB_tau_valid_i(6),  -- 36b
--  probe6(0)    =>  '0',  -- 36b
--  probe6(5 downto 1)     =>  XTOB_tau_valid_i(7),  -- 36b
--  probe6(10 downto 6)    =>  XTOB_eg_valid_i(6),  -- 36b
--  probe6(15 downto 11)   =>  XTOB_eg_valid_i(7),  -- 36b
--  probe6(35 downto 16)   =>  (others => '0'),        -- 36b
--  probe7(0) =>  '0',             -- 1b
--  probe8(0) =>  TOB_FIFO_sw_rst ,       -- 1b
--    probe9(0) =>  '0'              -- 1b
--);
 
end Behavioral;