cntr_generic Entity Reference

Generic Counter for process FPGA. More...

Inheritance diagram for cntr_generic:

Entities
Behavioral	architecture
	Generic Counter for process FPGA. More...

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
std_logic_arith

Generics
width	integer := 32
WRAPAROUND	boolean := True

Ports
CE	in	STD_LOGIC
		Enable signal input.
CLK	in	STD_LOGIC
		Clock signal input.
RST	in	STD_LOGIC
		Reset signal input.
Q	out	STD_LOGIC_VECTOR ( width- 1 downto 0 )
		Counter Output signal.

Detailed Description

Generic Counter for process FPGA.

This module is a Generic Counter. By default the output of counter goes to ZERO when it reaches full count, or if a RESET is applied, but with WRAPAROUND set to false the counter will saturate when it reaches full count

Author

Saeed Taghavi

Definition at line 16 of file cntr_generic.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/cntr_generic.vhd