Behavioral Architecture Reference

Generic Counter for process FPGA. More...

Processes
PROCESS_20	( CLK )

Detailed Description

Generic Counter for process FPGA.

This module is a Generic Counter. By default the output of counter goes to ZERO when it reaches full count, or if a RESET is applied, but with WRAPAROUND set to false the counter will saturate when it reaches full count

Author

Saeed Taghavi

Definition at line 34 of file cntr_generic.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/cntr_generic.vhd