Behavioral Architecture Reference

FSM to write Merged TOBs and Local XTOBs (tau & e/g) data to Link Output FIFO for process FPGA 1 and 2. More...

Processes
U1_clk_280_proc	( CLK_280M_i )
U3A_proc1	( CLK_280M_i )
U4_rd_fsm	( CLK_280M_i )

Constants
FPGA_mapping	FPGA_mapping_array := ( " 10 " , " 01 " , " 11 " , " 00 " )

Types
FPGA_mapping_array	( 3 downto 0 ) std_logic_vector ( 1 downto 0 )
STATE_TYPE	( idle , idle_1 , wait1 , wait2 , wait3 , wait4 , wait5 , err_sop , err_eop , norm_sop1 , norm_sop2 , norm_tlr , norm_eop , rd_fifo , sub_trl_1 , sub_trl_2 , rdout_T_TOB_eg , rdout_XTOB_eg_a0 , rdout_XTOB_eg_a , rdout_XTOB_eg_b , rdout_XTOB_tau_a0 , rdout_XTOB_tau_a , rdout_XTOB_tau_b )

Signals
TOB_out_valid_i	std_logic
TOB_rdout_fifo_rd_en_i	std_logic
corrective_trailer	std_logic
BCN_FIFO_rd_en_i	std_logic
BCN_FIFO_valid_in_i	std_logic
slice_count_i	unsigned ( 2 downto 0 ) := ( others = > ' 0 ' )
link_err_flg_in_i	STD_LOGIC_VECTOR ( 3 downto 0 ) := ( others = > ' 0 ' )
TOB_BCN_in_i	STD_LOGIC_VECTOR ( 7 downto 0 ) := ( others = > ' 0 ' )
FIFO_BCN_in_i	STD_LOGIC_VECTOR ( 11 downto 0 ) := ( others = > ' 0 ' )
XTOB_eg_BCN_in_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
XTOB_hdr_BCN_in_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
XTOB_tau_BCN_in_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
FIFO_L1A_ID_i	STD_LOGIC_VECTOR ( 23 downto 0 ) := ( others = > ' 0 ' )
FIFO_L1A_ID_EXT_i	STD_LOGIC_VECTOR ( 7 downto 0 ) := ( others = > ' 0 ' )
TOBs_out_i	STD_LOGIC_VECTOR ( 31 downto 0 ) := ( others = > ' 0 ' )
TOB_out_is_char_i	std_logic
write_in_LO_FIFO_i	std_logic
CLK_280M_i	std_logic
cntr_rst_i	std_logic
TOB_cntr_rst	std_logic
T_TOB_cntr_en_i	std_logic := ' 0 '
T_TOB_cntr_i	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
T_TOB_cntr_1dly	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
XTOB_eg_cntr_en_i	std_logic := ' 0 '
XTOB_eg_cntr_i	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
XTOB_eg_cntr_1dly	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
XTOB_tau_cntr_en_i	std_logic := ' 0 '
XTOB_tau_cntr_i	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
XTOB_tau_cntr_1dly	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
trailer_cntr_en	std_logic
payld_cntr_rst	std_logic
payld_cntr_rst_i	std_logic
payld_cntr_en	std_logic := ' 0 '
TOB_payld_cntr_i	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
TOB_payld_cntr_1dly	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
frame_cntr_en_i	std_logic
slice_no_txed	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
T_TOB_eg_i	std_logic_vector ( 191 downto 0 ) := ( others = > ' 0 ' )
T_TOB_eg_valid_i	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
valid_XTOBs_eg_i	std_logic
valid_XTOBs_tau_i	std_logic
XTOB_eg_i	array_8_of_240b
XTOB_eg_valid_i	array_8_of_5b
XTOB_tau_i	array_8_of_240b
XTOB_tau_valid_i	array_8_of_5b
safe_mode_i	std_logic
miss_sop_i	std_logic
wr_en_i	std_logic
current_state	STATE_TYPE
i	integer range 0 to 9
m_s_count	integer range 0 to 7

Attributes
keep	string
max_fanout	integer

Instantiations
u2_t_tob_cntr	cntr_generic <Entity cntr_generic>
u2_xtob_eg_cntr	cntr_generic <Entity cntr_generic>
u2_xtob_tau_cntr	cntr_generic <Entity cntr_generic>
u2_tob_payld_length	cntr_generic <Entity cntr_generic>

Detailed Description

FSM to write Merged TOBs and Local XTOBs (tau & e/g) data to Link Output FIFO for process FPGA 1 and 2.

This module creates a complete TOB/XTOB event together with Header and Trailer and writes the entire event into Link Output FIFO. The Link Output FIFO is then controlled by FIFO_to_MGT_FSM state machine to transfer data to MGT.

This FSM is generated to write TOBs and XTOBS into an event packet for pFPGA 1 and 2, and generated to write only XTOBS into an event packet for pFPGA 3 and 4

Process FPGA 1 construct events with merged e/g TOBs from all 4 Process FPGAs and local XTOBs. Process FPGA 2 construct events with merged tau TOBs from all 4 Process FPGAs and local XTOBs. Process FPGA 3 and 4 only construct events with their local XTOBs.

This FSM also handles Header and Trailer construction.

In order to create full TOB/XTOB event (frame) all parallel data from TOBs and XTOBs de-randomisation FIFOs must be read in turn, In multi-slice readout, all parallel data from TOB and XTOB de-randomisation FIFOs must be read twice or more.

When the occupancy of de-randomisation TOB/XTOB Data FIFO or TTC FIFO reaches its prog FULL occupancy level, a Safe Mode Flag is set which is used to create Safe Mode TOB/XTOB events and empty the TOB/XTOB Data FIFO & TTC FIFO. These Safe Mode events consists of 2 Header words, and one Trailer word. The payload consists of two words, a ZERO word together with a sub-trailer word for the slice. Multi-slice readout contains a number of these double words, equal to the number of slices to be readout.

1. Readout operation for Process FPGAs 1 & 2, create Events which consists of only Valid XTOB/TOBs.
   • TOB & XTOB Event in Normal Operation: Read 1 Slice - Takes 179 ticks of 280MHz clock to create one TOB & XTOB Event with 1 Slice Readout.
   • TOB & XTOB Event in Normal Operation: Read 2 Slice - Takes 352 ticks of 280MHz clock to create one TOB & XTOB Event with 2 Slice Readout.
   • TOB & XTOB Event in Normal Operation: Read 3 Slice - Takes 524 ticks of 280MHz clock to create one TOB & XTOB Event with 3 Slice Readout.
   • TOB & XTOB Event in Normal Operation: Read 4 Slice - Takes 697 ticks of 280MHz clock to create one TOB & XTOB Event with 4 Slice Readout.
   • TOB & XTOB Event in SAFE Mode Operation: Read 1 Slices - Takes 8 ticks of 280MHz clock to create one SAFE Mode TOB & XTOB Event. Read 2 Slices - Takes 12 ticks of 280MHz clock to create one SAFE Mode TOB & XTOB Event. etc.
2. Readout operation for Process FPGAs 3 & 4, create Events which consists of only Valid e/g and tau XTOBs..
   • XTOB Event in Normal Operation: Read 1 Slice - Takes 171 ticks of 280MHz clock to create one XTOB Event with 1 Slice Readout.
   • XTOB Event in Normal Operation: Read 2 Slice - Takes 344 ticks of 280MHz clock to create one XTOB Event with 2 Slice Readout.
   • XTOB Event in Normal Operation: Read 3 Slice - Takes 516 ticks of 280MHz clock to create one XTOB Event with 3 Slice Readout.
   • XTOB Event in Normal Operation: Read 4 Slice - Takes 691 ticks of 280MHz clock to create one XTOB Event with 4 Slice Readout.
   • XTOB Event in SAFE Mode Operation: Read 1 Slice - Takes 8 ticks of 280MHz clock to create one SAFE Mode XTOB Event. Read 2 Slice - Takes 12 ticks of 280MHz clock to create one SAFE Mode XTOB Event.

The output of this FSM is:

• 32-bit data word
• 1-bit data is CHAR
• 1-bit valid which is the write enable to Link Output FIFO

Header Word 1:

• TOBs_out_i(31:24) = TOB BCN
• TOBs_out_i(23:20) = XTOB BCN
• TOBs_out_i(19:8) = Local (internal) BCN
• TOBs_out_i(7:0) = ch_sop = X"3C"

Header Word 2:

• TOBs_out_i(31:24) = Extended L1_ID
• TOBs_out_i(23:0) = Level 1 ID

Trailer Word 1: Slice Trailer

• TOBs_out_i(31) = ZERO
• TOBs_out_i(30) = link_err_flg_in_i
• TOBs_out_i(29:28) = FPGA_mapping
• TOBs_out_i(27) = safe mode
• TOBs_out_i(26:24) = slice number transmitted
• TOBs_out_i(23:18) = XTOB counter tau
• TOBs_out_i(17:12) = XTOB counter e/g
• TOBs_out_i(11:9) = TOB counter
• TOBs_out_i(8) = TOB type in
• TOBs_out_i(7:0) = slice_end = X"5C" (K28.2)

Trailer Word 2: Event Trailer

• TOBs_out_i(31) = safe mode
• TOBs_out_i(30:27) = ZERO
• TOBs_out_i(26:24) = DPR_locations_to_rd (number of slices to read)
• TOBs_out_i(23:20) = trigger slice number
• TOBs_out_i(19:8) = TOB payload counter
• TOBs_out_i(7:0) = ch_eop = X"DC"

CHAR constants are defined in data_type_pkg.vhd

• for reference only
  • constant ch_idle : std_logic_vector(7 downto 0) := X"BC" ; – idle char is K28.5
  • constant ch_sop1 : std_logic_vector(7 downto 0) := X"3C" ; – TOB/XTOB star of packet char is K28.1
  • constant ch_sop2 : std_logic_vector(7 downto 0) := X"7C" ; – CALO DATA star of packet char is K28.3
  • constant ch_eop : std_logic_vector(7 downto 0) := X"DC" ; – end of packet char is K28.6
  • constant slice_end : std_logic_vector(7 downto 0) := X"5C" ; – end of slice char is K28.2

TRIGGER SLICE:

• identifies the slice number on L1A, as a number between 0 to 4
• TOB packet header word gets TOB/XTOB BCN from actual trigger slice TOB/XTOB data, but internal BCN from L1A_TOB FIFO
• L1A_TOB BCN is always the BCN on L1A, and must match TOB/XTOB BCN of Trigger Slice value

Author

Saeed Taghavi

Definition at line 191 of file fsm_TOBs_to_muxPISO.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/fsm_TOBs_to_muxPISO.vhd