FIFO_to_MGT_TOB_FSM Entity Reference

FSM to read TOB/XTOB data from Link Output FIFO for process FPGA. More...

Inheritance diagram for FIFO_to_MGT_TOB_FSM:

Entities
Behavioral	architecture
	FSM to read TOB/XTOB data from Link Output FIFO for process FPGA. More...

Libraries
IEEE
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>

Ports
TOB_FIFO_sw_rst	in	std_logic
		TOB Readout FIFO reset Pulse by software command.
clk_in_280M	in	STD_LOGIC
ctrl_TOB_ready_in	in	std_logic
		Ready signal from control FPGA to receive data from process FPGA.
frame_counter	in	STD_LOGIC_VECTOR ( 11 downto 0 )
		Frame counter register.
FIFO_MGT_TOBs	in	STD_LOGIC_VECTOR ( 32 downto 0 )
		TOB/XTOBs from Link Output FIFO.
FIFO_MGT_TOB_valid	in	STD_LOGIC
		TOB/XTOBs from Link Output FIFO valid signal.
MGT_FIFO_empty	in	std_logic
		Link Output FIFO Empty Flag.
FIFO_MGT_rd_en	out	STD_LOGIC
		Read enalbe singal to Link Output FIFO.
frame_counter_dec_en	out	STD_LOGIC
		Decrement Frame Counter.
T_TOBs_out	out	STD_LOGIC_VECTOR ( 31 downto 0 )
		32b TOB/XTOB to connect to output MGT to control FPGA
T_TOB_is_char	out	STD_LOGIC
		TOB/XTOB is CHAR to connect to output MGT to control FPGA.
T_TOB_out_valid	out	STD_LOGIC
		TOB/XTOB is valid signal to wr to SPY memory.
tob_data_mgt_fsm	out	STD_LOGIC_VECTOR ( 7 downto 0 )
		Monitor state machine status register.

Detailed Description

FSM to read TOB/XTOB data from Link Output FIFO for process FPGA.

This module reads a complete TOB/XTOB event together with Header and Trailer and writes the entire event into the MGT.

The frame counter is incremented/decremented as events are written/read from the Link_output FIFO.

This FSM reads TOB/XTOB frames from Link Output FIFO and writes into MGT to transmit to cFPGA.

This FSM handles one full frame at a time without pausing.

It monitors the TOB frame counter to find out if there are Frames waiting to be transmitted to cFPGA.

The Frames are only transmitted when cFPGA indicates it is ready to receive data by setting ctrl_TOB_ready signal to 1.

If ctrl_TOB_ready signal is set to 0 by cFPGA, this indicates cFPGA is not ready to receive data, in this case events accumulate in Link Output FIFO until occupancy reaches a pre-define prog_FULL level, at this time, Link Output FIFO stops receiving data.

Author

Saeed Taghavi

Definition at line 35 of file FIFO_to_MGT_TOB_FSM.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/FIFO_to_MGT_TOB_FSM.vhd