eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

Back to eFEX documentation
FIFO_to_MGT_TOB_FSM.vhd
Go to the documentation of this file.
1 
21 
22 
23 library IEEE;
24 use IEEE.STD_LOGIC_1164.ALL;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 use IEEE.NUMERIC_STD.ALL;
29 
30 library TOB_rdout_lib;
31 use TOB_rdout_lib.TOB_rdout_ip_pkg.ALL;
32 use TOB_rdout_lib.data_type_pkg.all;
33 
35 entity FIFO_to_MGT_TOB_FSM is
36  Port (
38  TOB_FIFO_sw_rst : in std_logic ;
39  clk_in_280M : in STD_LOGIC;
41  ctrl_TOB_ready_in : in std_logic ;
43  frame_counter : in STD_LOGIC_VECTOR (11 downto 0);
45  FIFO_MGT_TOBs : in STD_LOGIC_VECTOR (32 downto 0);
47  FIFO_MGT_TOB_valid : in STD_LOGIC;
49  MGT_FIFO_empty : in std_logic;
51  FIFO_MGT_rd_en : out STD_LOGIC;
53  frame_counter_dec_en : out STD_LOGIC;
55  T_TOBs_out : out STD_LOGIC_VECTOR (31 downto 0);
57  T_TOB_is_char : out STD_LOGIC;
59  T_TOB_out_valid : out STD_LOGIC;
61  tob_data_mgt_fsm : out STD_LOGIC_VECTOR (7 downto 0)
62  );
63 end FIFO_to_MGT_TOB_FSM;
64 
66 architecture Behavioral of FIFO_to_MGT_TOB_FSM is
67 
68 -- CHAR constants are defined in data_type_pkg.vhd
69 -- for reference only
70 -- constant ch_idle : std_logic_vector(7 downto 0) := X"BC" ; -- idle char is K28.5
71 -- constant ch_sop1 : std_logic_vector(7 downto 0) := X"3C" ; -- star of packet char 1 is K28.1
72 -- constant ch_sop2 : std_logic_vector(7 downto 0) := X"5C" ; -- star of packet char 2 is K28.2
73 -- constant ch_eop : std_logic_vector(7 downto 0) := X"DC" ; -- end of packet char is K28.6
74 
75 --************************** Register Declarations ****************************
76  signal clk_in_280M_i : STD_LOGIC;
77 
78  signal T_TOB_out_valid_i : STD_LOGIC;
79  signal TOB_in_is_char_i : STD_LOGIC;
80  signal TOBs_in_i : STD_LOGIC_VECTOR (31 downto 0);
81  signal MGT_fifo_rd_en_i : STD_LOGIC;
82  signal TOBs_out_i, TOBs_in_tmp_1dly : STD_LOGIC_VECTOR (31 downto 0);
83  signal TOB_out_is_char_i, TOB_in_is_char_tmp_1dly : STD_LOGIC;
84 
85  signal frame_counter_dec_en_i : STD_LOGIC;
86 
87 
88  TYPE STATE_TYPE IS (
89  idle, rd_fifo1, rd_fifo2, tx_data_SOF1, tx_data_SOF2, tx_data1, tx_data2, tx_data_EOF1, tx_data_EOF2,
90  wait1, wait2, wait3, wait4
91  );
92 
93  SIGNAL current_state : STATE_TYPE;
94 
95 begin
96  -- input ports
97  clk_in_280M_i <= clk_in_280M ;
98 
99  -- output port
100 -- T_TOBs_out <= TOBs_out_i; -- TOB data out to MGT
101 -- T_TOB_is_char <= TOB_out_is_char_i ; -- TOB data out to MGT is CHAR
102 -- T_TOB_out_valid <= T_TOB_out_valid_i ; -- TOB data out is valid
103  FIFO_MGT_rd_en <= MGT_fifo_rd_en_i ;
104 
105  -- output ports
106 -- frame_counter_dec_en <= frame_counter_dec_en_i ;
107 
108 
109 U1_clk_proc : process (clk_in_280M_i) -- to remove timing errors
110  begin
111  if clk_in_280M_i'event and clk_in_280M_i = '1' then
112  -- output ports
113  T_TOBs_out <= TOBs_out_i; -- TOB data out to MGT
114  T_TOB_is_char <= TOB_out_is_char_i ; -- TOB data out to MGT is CHAR
115  T_TOB_out_valid <= T_TOB_out_valid_i ; -- TOB data out is valid
116 -- FIFO_MGT_rd_en <= MGT_fifo_rd_en_i ;
117 
118  frame_counter_dec_en <= frame_counter_dec_en_i ;
119  end if;
120  end process;
121 
122 U2_clk_proc : process (clk_in_280M_i) -- to remove timing errors
123  begin
124  if clk_in_280M_i'event and clk_in_280M_i = '1' then
125  if MGT_fifo_rd_en_i = '1' then
126  TOB_in_is_char_tmp_1dly <= FIFO_MGT_TOBs(32); -- TOB data from FIFO is CHAR
127  TOBs_in_tmp_1dly <= FIFO_MGT_TOBs(31 downto 0); -- TOB is char from FIFO
128  end if;
129  end if;
130  end process;
131 
132 -- TOB_in_is_char_tmp_1dly <= FIFO_MGT_TOBs(32); -- TOB data from FIFO is CHAR
133 -- TOBs_in_tmp_1dly <= FIFO_MGT_TOBs(31 downto 0); -- TOB data from FIFO
134 
135 U4_rd_fsm : process (clk_in_280M_i)
136  begin
137 -- MGT_FIFO_empty_i <= MGT_FIFO_empty ; -- cater for the empty going high on last word
138  if clk_in_280M_i'event and clk_in_280M_i = '1' then
139  if ( TOB_FIFO_sw_rst = '1' )then -- signal is RST OR TOB_FIFO_sw_rst
140  TOB_in_is_char_i <= '0';
141  TOBs_in_i <= (others => '0');
142  current_state <= idle ;
143  else
144  TOB_in_is_char_i <= TOB_in_is_char_tmp_1dly; -- TOB data from FIFO is CHAR
145  TOBs_in_i <= TOBs_in_tmp_1dly(31 downto 0); -- TOB data from FIFO
146  T_TOB_out_valid_i <= '0';
147  tob_data_mgt_fsm <= X"00";
148 
149  CASE current_state is
150  when idle =>
151  tob_data_mgt_fsm <= X"01";
152  T_TOB_out_valid_i <= '0' ;
153  frame_counter_dec_en_i <= '0' ;
154  MGT_fifo_rd_en_i <= '0' ;
155  TOB_out_is_char_i <= '1';
156  TOBs_out_i <= X"000000" & ch_idle ; -- K28.5 idle = BC
157  -- if no data available wait
158  if ctrl_TOB_ready_in = '1' then -- if CNTL FPGA ready to receive data
159  if (frame_counter > X"000" ) then
160  -- if FRAME fifo is not empty, read DATA fifos
161  current_state <= rd_fifo1 ;
162  end if;
163  end if;
164 
165  when rd_fifo1 =>
166  T_TOB_out_valid_i <= '0' ;
167  TOB_out_is_char_i <= '1';
168  TOBs_out_i <= X"000000" & ch_idle ; -- K28.5 idle
169  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
170  tob_data_mgt_fsm <= X"02";
171  if (TOBs_in_tmp_1dly(7 downto 0) = X"3C" AND TOB_in_is_char_tmp_1dly = '1') then -- check fist data in order to save the SOF data and char
172  current_state <= tx_data_SOF1 ;
173  else
174  -- if fifo is not empty, read fifos
175  current_state <= rd_fifo1 ;
176  end if;
177 
178  when tx_data_SOF1 =>
179  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
180  TOB_out_is_char_i <= TOB_in_is_char_i;
181  TOBs_out_i <= TOBs_in_i ;
182  T_TOB_out_valid_i <= '1' ;
183  current_state <= tx_data1 ;
184  tob_data_mgt_fsm <= X"03";
185 
186  when wait3 => -- this is a FIFO rd to ensure correct SOF
187  T_TOB_out_valid_i <= '0' ;
188  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
189  TOB_out_is_char_i <= '1';
190  TOBs_out_i <= X"000000"& ch_idle ; -- K28.5 idle
191  current_state <= wait4 ; -- was
192  tob_data_mgt_fsm <= X"04";
193 
194  when wait4 => -- this is a FIFO rd to ensure correct SOF
195  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
196  TOB_out_is_char_i <= TOB_in_is_char_i;
197  TOBs_out_i <= TOBs_in_i ;
198  T_TOB_out_valid_i <= '1' ;
199  current_state <= tx_data1 ; -- was
200 
201  when tx_data1 =>
202  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
203  TOB_out_is_char_i <= TOB_in_is_char_i;
204  TOBs_out_i <= TOBs_in_i ;
205  T_TOB_out_valid_i <= '1' ;
206  tob_data_mgt_fsm <= X"05";
207  if (TOBs_in_tmp_1dly(7 downto 0) = X"DC" AND TOB_in_is_char_tmp_1dly = '1') then -- check last data in order to save the SOF data and char
208  frame_counter_dec_en_i <= '1' ;
209  MGT_fifo_rd_en_i <= '0'; -- read data from fifos
210  current_state <= tx_data_EOF1 ;
211  else
212  -- MGT_fifo_rd_en_i <= '1'; -- read data from fifos
213  -- if fifo is not empty, read fifos
214  current_state <= tx_data1 ;
215  end if;
216 
217  when tx_data_EOF1 =>
218  frame_counter_dec_en_i <= '0' ;
219  TOB_out_is_char_i <= TOB_in_is_char_i;
220  TOBs_out_i <= TOBs_in_i ;
221  T_TOB_out_valid_i <= '1' ;
222  current_state <= wait1 ; -- was
223  tob_data_mgt_fsm <= X"06";
224 
225  when wait1 =>
226  T_TOB_out_valid_i <= '0' ;
227  TOB_out_is_char_i <= '1';
228  TOBs_out_i <= X"000000"& ch_idle ; -- K28.5 idle
229  current_state <= wait2 ; -- was
230 
231  when wait2 =>
232  T_TOB_out_valid_i <= '0' ;
233  TOB_out_is_char_i <= '1';
234  TOBs_out_i <= X"000000"& ch_idle ; -- K28.5 idle
235  current_state <= tx_data_EOF2 ; -- was
236 
237  when tx_data_EOF2 =>
238  T_TOB_out_valid_i <= '0' ;
239  TOB_out_is_char_i <= '1';
240  TOBs_out_i <= X"000000" & ch_idle ; -- K28.5 idle
241  current_state <= tx_data_EOF2 ;
242  tob_data_mgt_fsm <= X"07";
243  if ctrl_TOB_ready_in = '1' then
244  if (frame_counter = X"000" ) then -- if frame_counter = X"000"
245  if (TOBs_in_i(7 downto 0) = X"DC" AND TOB_in_is_char_i = '1') then -- no event is in FIFO (end of last event)
246  current_state <= idle ;
247  end if;
248  else -- if frame_counter /= X"000"
249  MGT_fifo_rd_en_i <= '1'; -- read data from fifos
250  if (TOBs_in_i(7 downto 0) = X"3C" AND TOB_in_is_char_i = '1') then -- more events are in FIFO (start of next event)
251  current_state <= wait3 ;
252  end if;
253  end if;
254  end if;
255 
256  when others =>
257  NULL;
258  end case;
259  end if;
260  end if;
261  end process;
262 
263 end Behavioral;
FIFO_to_MGT_TOB_FSM.Behavioral
FSM to read TOB/XTOB data from Link Output FIFO for process FPGA.
Definition: FIFO_to_MGT_TOB_FSM.vhd:66
FIFO_to_MGT_TOB_FSM
FSM to read TOB/XTOB data from Link Output FIFO for process FPGA.
Definition: FIFO_to_MGT_TOB_FSM.vhd:35
FIFO_to_MGT_TOB_FSM.tob_data_mgt_fsm
out tob_data_mgt_fsm STD_LOGIC_VECTOR( 7 downto 0)
Monitor state machine status register.
Definition: FIFO_to_MGT_TOB_FSM.vhd:62
FIFO_to_MGT_TOB_FSM.frame_counter
in frame_counter STD_LOGIC_VECTOR( 11 downto 0)
Frame counter register.
Definition: FIFO_to_MGT_TOB_FSM.vhd:43
FIFO_to_MGT_TOB_FSM.FIFO_MGT_TOBs
in FIFO_MGT_TOBs STD_LOGIC_VECTOR( 32 downto 0)
TOB/XTOBs from Link Output FIFO.
Definition: FIFO_to_MGT_TOB_FSM.vhd:45
FIFO_to_MGT_TOB_FSM.FIFO_MGT_rd_en
out FIFO_MGT_rd_en STD_LOGIC
Read enalbe singal to Link Output FIFO.
Definition: FIFO_to_MGT_TOB_FSM.vhd:51
FIFO_to_MGT_TOB_FSM.T_TOB_out_valid
out T_TOB_out_valid STD_LOGIC
TOB/XTOB is valid signal to wr to SPY memory.
Definition: FIFO_to_MGT_TOB_FSM.vhd:59
FIFO_to_MGT_TOB_FSM.T_TOBs_out
out T_TOBs_out STD_LOGIC_VECTOR( 31 downto 0)
32b TOB/XTOB to connect to output MGT to control FPGA
Definition: FIFO_to_MGT_TOB_FSM.vhd:55
FIFO_to_MGT_TOB_FSM.ctrl_TOB_ready_in
in ctrl_TOB_ready_in std_logic
Ready signal from control FPGA to receive data from process FPGA.
Definition: FIFO_to_MGT_TOB_FSM.vhd:41
FIFO_to_MGT_TOB_FSM.frame_counter_dec_en
out frame_counter_dec_en STD_LOGIC
Decrement Frame Counter.
Definition: FIFO_to_MGT_TOB_FSM.vhd:53
FIFO_to_MGT_TOB_FSM.T_TOB_is_char
out T_TOB_is_char STD_LOGIC
TOB/XTOB is CHAR to connect to output MGT to control FPGA.
Definition: FIFO_to_MGT_TOB_FSM.vhd:57
FIFO_to_MGT_TOB_FSM.MGT_FIFO_empty
in MGT_FIFO_empty std_logic
Link Output FIFO Empty Flag.
Definition: FIFO_to_MGT_TOB_FSM.vhd:49
FIFO_to_MGT_TOB_FSM.TOB_FIFO_sw_rst
in TOB_FIFO_sw_rst std_logic
TOB Readout FIFO reset Pulse by software command.
Definition: FIFO_to_MGT_TOB_FSM.vhd:38
FIFO_to_MGT_TOB_FSM.FIFO_MGT_TOB_valid
in FIFO_MGT_TOB_valid STD_LOGIC
TOB/XTOBs from Link Output FIFO valid signal.
Definition: FIFO_to_MGT_TOB_FSM.vhd:47
TOB_rdout_ip_pkg
Definition: TOB_rdout_ip_pkg.vhd:34
data_type_pkg
Definition: data_type_pkg.vhd:34
Generated on Tue Nov 11 2025 09:44:32 for eFEX firmware by   doxygen 1.9.1