Behavioral Architecture Reference

FSM to read TOB/XTOB data from Link Output FIFO for process FPGA. More...

Processes
U1_clk_proc	( clk_in_280M_i )
U2_clk_proc	( clk_in_280M_i )
U4_rd_fsm	( clk_in_280M_i )

Types
STATE_TYPE	( idle , rd_fifo1 , rd_fifo2 , tx_data_SOF1 , tx_data_SOF2 , tx_data1 , tx_data2 , tx_data_EOF1 , tx_data_EOF2 , wait1 , wait2 , wait3 , wait4 )

Signals
clk_in_280M_i	STD_LOGIC
T_TOB_out_valid_i	STD_LOGIC
TOB_in_is_char_i	STD_LOGIC
TOBs_in_i	STD_LOGIC_VECTOR ( 31 downto 0 )
MGT_fifo_rd_en_i	STD_LOGIC
TOBs_out_i	STD_LOGIC_VECTOR ( 31 downto 0 )
TOBs_in_tmp_1dly	STD_LOGIC_VECTOR ( 31 downto 0 )
TOB_out_is_char_i	STD_LOGIC
TOB_in_is_char_tmp_1dly	STD_LOGIC
frame_counter_dec_en_i	STD_LOGIC
current_state	STATE_TYPE

Detailed Description

FSM to read TOB/XTOB data from Link Output FIFO for process FPGA.

This module reads a complete TOB/XTOB event together with Header and Trailer and writes the entire event into the MGT.

The frame counter is incremented/decremented as events are written/read from the Link_output FIFO.

This FSM reads TOB/XTOB frames from Link Output FIFO and writes into MGT to transmit to cFPGA.

This FSM handles one full frame at a time without pausing.

It monitors the TOB frame counter to find out if there are Frames waiting to be transmitted to cFPGA.

The Frames are only transmitted when cFPGA indicates it is ready to receive data by setting ctrl_TOB_ready signal to 1.

If ctrl_TOB_ready signal is set to 0 by cFPGA, this indicates cFPGA is not ready to receive data, in this case events accumulate in Link Output FIFO until occupancy reaches a pre-define prog_FULL level, at this time, Link Output FIFO stops receiving data.

Author

Saeed Taghavi

Definition at line 66 of file FIFO_to_MGT_TOB_FSM.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/FIFO_to_MGT_TOB_FSM.vhd