gen_sync_280M.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
library TOB_rdout_lib;
 
library UNISIM;
use UNISIM.VComponents.all;
 
entity gen_sync_280M is
    Port ( 
        RST             : in STD_LOGIC;
        clk_40M         : in STD_LOGIC;
        clk_280M        : in STD_LOGIC;
        sync_280m_out   : out STD_LOGIC
        );
end gen_sync_280M;
 
architecture Behavioral of gen_sync_280M is
 
    signal LoadR     : std_logic := '0';
    signal LoadF     : std_logic := '0';
    signal Load      : std_logic := '0';
 
begin
 
   process(clk_40M)
   begin
     if rising_edge(clk_40M) then 
        if RST = '0' then
            LoadR <= not LoadR;
        end if;
     end if;
   end process;
 
   process(clk_280M)
   begin
     if rising_edge(clk_280M) then
        if RST = '0' then
            LoadF <= LoadR;
            Load <= LoadR xor LoadF; -- move this inside the clocked process
        end if;
     end if;
   end process;
 
 
   sync_280m_out <= Load; 
 
end Behavioral;