Behavioral Architecture Reference

Generate Synch at 280MHz. More...

Processes
PROCESS_25	( clk_40M )
PROCESS_26	( clk_280M )

Signals
LoadR	std_logic := ' 0 '
LoadF	std_logic := ' 0 '
Load	std_logic := ' 0 '

Detailed Description

Generate Synch at 280MHz.

This module generates a synch signal synchronised to 40MHz and 280MHz clocks one synch pulse is generated - this is 1 in 7 sync'ed to 40M clock

280 MHz to 40 MHz Synch Diagram

Author

Saeed Taghavi

Definition at line 34 of file gen_sync_280M.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/gen_sync_280M.vhd