gen_sync_280M Entity Reference

Generate Synch at 280MHz. More...

Inheritance diagram for gen_sync_280M:

Entities
Behavioral	architecture
	Generate Synch at 280MHz. More...

Libraries
IEEE
TOB_rdout_lib
UNISIM

Use Clauses
STD_LOGIC_1164
VComponents

Ports
RST	in	STD_LOGIC
		Reset in.
clk_40M	in	STD_LOGIC
		Clock 40MHz in.
clk_280M	in	STD_LOGIC
		Clock 2800MHz in.
sync_280m_out	out	STD_LOGIC
		280MHz synch signal output

Detailed Description

Generate Synch at 280MHz.

This module generates a synch signal synchronised to 40MHz and 280MHz clocks one synch pulse is generated - this is 1 in 7 sync'ed to 40M clock

280 MHz to 40 MHz Synch Diagram

Author

Saeed Taghavi

Definition at line 20 of file gen_sync_280M.vhd.

---

The documentation for this class was generated from the following file:

• Readout/src/gen_sync_280M.vhd