cntr_up_dn_generic.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
 
entity cntr_up_dn_generic is
    generic (
        width  : integer := 16
        );
    Port ( 
       CE   : in STD_LOGIC;
       CLK  : in STD_LOGIC;
       RST  : in STD_LOGIC;
       UP   : in STD_LOGIC;
       DOWN : in STD_LOGIC;
       Q    : out STD_LOGIC_VECTOR (width-1 downto 0)
       );
end cntr_up_dn_generic;
 
architecture Behavioral of cntr_up_dn_generic is
 
    signal temp : unsigned (width-1 downto 0) ;
 
begin
process (CLK)
    begin
    if CLK'event AND CLK = '1' then
        if RST = '1' then             -- this is a synchronous reset 
            temp <= (others => '0');              -- set counter to offset value given.
        else
            if UP = '1' AND DOWN = '0'then
                    temp <= temp + 1;                     -- else increment the value by one 
            else
                if UP = '0' AND DOWN = '1' then 
                    if temp > 0 then         -- if count > 0
                        temp <= temp - 1;       -- else decrement the value by one 
                    end if;
                else
                    temp <= temp;   -- do nothing
                end if;
            end if;
        end if;
    end if;
    end process;
    Q <= std_logic_vector(temp) ;    -- push out new value
 
end Behavioral;