cntr_up_dn_generic Entity Reference

Up/Down counter. More...

Inheritance diagram for cntr_up_dn_generic:

Entities
Behavioral	architecture
	Up/Down counter. More...

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
std_logic_arith

Generics
width	integer := 16

Ports
CE	in	STD_LOGIC
		Enable signal input.
CLK	in	STD_LOGIC
		Clock signal input.
RST	in	STD_LOGIC
		Reset signal input.
UP	in	STD_LOGIC
		Count UP signal input.
DOWN	in	STD_LOGIC
		Count DOWN signal input.
Q	out	STD_LOGIC_VECTOR ( width- 1 downto 0 )
		Counter Output signal.

Detailed Description

Up/Down counter.

This is a generic Up/Down counter. The frame counter is incremented when EN and UP signals are asserted, and decremented when EN and DOWN signals are asserted. If Read and Write happen on the same clock cycle, the ouptut of counter does not change.

Author

Saeed Taghavi

Definition at line 18 of file cntr_up_dn_generic.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/cntr_up_dn_generic.vhd