T_TOBs_sorting Entity Reference

Top of Sorting_TOBs module for process FPGA. More...

Inheritance diagram for T_TOBs_sorting:

Entities
RTL	architecture
	Top of Sorting_TOBs module for process FPGA. More...

Libraries
ieee
UNISIM
TOB_rdout_lib

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>

Generics
FPGA_NUMBER	integer := 1
	Integer used to distinguish different FPGAs having a slightly different firmware.

Ports
L1A_in	in	STD_LOGIC
		L1A signal input.
TOB_FIFO_sw_rst	in	std_logic
		TOB Readout FIFO reset Pulsed by software command.
TOBs_32b_in	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Sorted TOBs 32b * 7 in series.
TOBs_sync_in	in	STD_LOGIC
		Sorted TOB synch signal - indicating the start of the 7 TOB data words.
TOBs_valid_flg_in	in	STD_LOGIC
		Sorted TOB valid signal - used to write TOBs into de-randomisation TOB FIFO.
ALGO_TOB_BCN_in	in	std_logic_vector ( 6 downto 0 )
		Sorted TOB BCN with delay through ALGO/sorting block.
FIFO_rd_en	in	STD_LOGIC
		Read sorted TOB data from de-randomisation TOB FIFO into TOB Link Output FIFO.
clk_280M_in	in	STD_LOGIC
		280Mhz input signal
pre_ld_wr_addr_TOB	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		Latency pre-load for TOB Circular DRPAM write address.
DPR_locations_to_rd	in	STD_LOGIC_VECTOR ( 2 downto 0 )
		Number of multi-slice locations to read from DPRAM.
trigger_slice_in	in	STD_LOGIC_VECTOR ( 3 downto 0 )
		Trigger slice number - on L1A.
TOBs_FIFO_pFULL_THRESH_assert	in	STD_LOGIC_VECTOR ( 8 DOWNTO 0 )
		Threshold to assert FIFO prog full flag.
TOBs_FIFO_pFULL_THRESH_negate	in	STD_LOGIC_VECTOR ( 8 DOWNTO 0 )
		Threshold to de-assert FIFO prog full flag.
rdout_T_TOB_209b	out	STD_LOGIC_VECTOR ( 208 downto 0 )
		Sorted TOBs output of fifo 209b = 7b TOB_BCN +4b error+6b valid +192b TOB data.
TOBs_FIFO_data_count	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		Sorted TOBs FIFO occupancy count.
TOBs_data_full	out	STD_LOGIC
		Sorted TOBs FIFO full flag.
TOBs_data_empty	out	STD_LOGIC
		Sorted TOBs FIFO empty flag.
TOBs_data_valid	out	STD_LOGIC
		Sorted TOBs FIFO data valid signal.
TOBs_data_prog_full	out	STD_LOGIC
		Sorted TOBs FIFO prog full flag.
tob_data_dpram_fsm	out	STD_LOGIC_VECTOR ( 7 downto 0 )
		Monitor state machine status register.

Detailed Description

Top of Sorting_TOBs module for process FPGA.

This module receives 7 x 32-bit Merged TOBs together with 7 valid signals in series, and sorts them into a 6 x 32-bit parallel word and 6 bit valid word to store in Circular DPRAM. The 7th TOB is ignored as a trailer is added to transfer the data to TOPO. In order to be able to read multi-slices, the TOBs and XTOBs must be converted into long parallel data words.

This module is only instantiated for Process FPGA 1 and 2, and is disabled for Process FPGA 3 and 4.

Only Process FPGA 1 and 2 transmit e/g and tau events to TOPO, and the off-line Readout, but Process FPGA 3 and 4 do not transmit to TOPO instead they send their TOBs to Process FPGA 1 and 2. Process FPGA 3 and 4 transmit XTOB only events to the Control FPGA.

The FSM then reads data from DPRAM into FIFO upon arrival of L1A The SIPO data is 209b = 7b TOB_BCN +4b error+6b valid +192b TOB data. The SIPO data of 209b is saved every BC tick to enable multi-slice readout.

Author

Saeed Taghavi

Definition at line 33 of file T_TOBs_sorting.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/T_TOBs_sorting.vhd