T_TOBs_sorting.vhd

Go to the documentation of this file.

 
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
 
library TOB_rdout_lib;
use TOB_rdout_lib.TOB_rdout_ip_pkg.ALL;
 
entity T_TOBs_sorting is
    Generic
        ( 
    FPGA_NUMBER : integer := 1
        ) ; 
    Port ( 
       L1A_in                : in STD_LOGIC;
       TOB_FIFO_sw_rst           : in std_logic ;       
       TOBs_32b_in             : in STD_LOGIC_VECTOR (31 downto 0);   
       TOBs_sync_in            : in STD_LOGIC;                        
       TOBs_valid_flg_in       : in STD_LOGIC;                        
       ALGO_TOB_BCN_in         : in std_logic_vector(6 downto 0);
       FIFO_rd_en               : in STD_LOGIC;                        
       clk_280M_in              : in STD_LOGIC;
       pre_ld_wr_addr_TOB        : in STD_LOGIC_VECTOR (8 downto 0);
       DPR_locations_to_rd   : in STD_LOGIC_VECTOR (2 downto 0); 
       trigger_slice_in       : in STD_LOGIC_VECTOR(3 downto 0) ;   
       TOBs_FIFO_pFULL_THRESH_assert     : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
       TOBs_FIFO_pFULL_THRESH_negate     : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
       rdout_T_TOB_209b         : out STD_LOGIC_VECTOR (208 downto 0);    
       TOBs_FIFO_data_count     : out STD_LOGIC_VECTOR (8 downto 0) ; 
       TOBs_data_full           : out STD_LOGIC;
       TOBs_data_empty          : out STD_LOGIC;
       TOBs_data_valid          : out STD_LOGIC;
       TOBs_data_prog_full      : out STD_LOGIC;
       tob_data_dpram_fsm        : out STD_LOGIC_VECTOR (7 downto 0)
       
       );
    end T_TOBs_sorting;
 
architecture RTL of T_TOBs_sorting is
 
--************************** Register Declarations ****************************    
 
    signal  clk_in_280M_i          : STD_LOGIC;
    -- Sorted TOBs signals
    signal  SIPO_T_TOB_out_i       : STD_LOGIC_VECTOR (191 downto 0);   -- T_TOBs 32b * 6 = 192
    signal  SIPO_T_TOB_sync_out_i  : STD_LOGIC;                 
    signal  T_TOB_valid_out_i      : STD_LOGIC_VECTOR (5 downto 0);     -- T TOBs valid 6b (ignore 7th TOB)
                     
    signal  DPR_T_TOBs_in_i         : STD_LOGIC_VECTOR (208 downto 0);  -- 209b = 7b TOB_BCN +4b error+6b valid +192b data
    signal  DPR_T_TOBs_out_i        : STD_LOGIC_VECTOR (208 downto 0);  -- 209b = 7b TOB_BCN +4b error+6b valid +192b data 
    signal  rdout_T_TOB_209b_i        : STD_LOGIC_VECTOR (208 downto 0);  -- 209b = 7b TOB_BCN +4b error+6b valid +192b data 
 
    signal  DPR_T_TOB_rd_addr_i     : STD_LOGIC_VECTOR (8 downto 0);
    signal  DPR_T_TOB_wr_addr_i     : STD_LOGIC_VECTOR (8 downto 0);
    signal  DRP_T_TOB_rd_en_i       : std_logic ;
    
    signal  SIPO_T_TOB_sync_vec_i   : STD_LOGIC_VECTOR (0 downto 0);
    signal  FIFO_wr_en_i, L1A_in_i  : std_logic;
    signal  FIFO_wr_en_tmp          : std_logic ;
 
    signal  ALGO_TOB_BCN_out_i      : std_logic_vector (6 downto 0); -- sorted TOB BCN with delay through ALGO/sorting block
    signal  TOBs_FIFO_data_count_i  :STD_LOGIC_VECTOR (8 downto 0) ;
    signal  tied_to_vcc_i           : std_logic;
    signal  TOBs_data_valid_i       : std_logic;
    signal  TOBs_data_prog_full_i, TOBs_data_full_i, TOBs_data_empty_i            : std_logic;
 
begin
 
    tied_to_vcc_i  <=   '1';
 
    clk_in_280M_i  <= clk_280M_in ;  
    
-- output signals:
       FIFO_wr_en_tmp           <= FIFO_wr_en_i  ; 
       L1A_in_i                 <= L1A_in ;      
 
-- register output of FIFO to remove timing violations - use ALGO Block 4 to be middle of FPGA
U6_TOB_clk280_proc : Process (clk_in_280M_i)
begin
    if rising_edge (clk_in_280M_i) then
       rdout_T_TOB_209b         <= rdout_T_TOB_209b_i ;
       TOBs_FIFO_data_count     <= TOBs_FIFO_data_count_i ; 
       TOBs_data_full           <= TOBs_data_full_i;
       TOBs_data_empty          <= TOBs_data_empty_i;
       TOBs_data_valid          <= TOBs_data_valid_i;
       TOBs_data_prog_full      <= TOBs_data_prog_full_i;
    end if;
end process;
 
-- SIPO for Sorted TOBs module is responsible for generating a parallel word,
-- consisting of 6 x 32-bit TOBs and 6 valid flags.
-- 
U1_TOBs_eg : entity TOB_rdout_lib.SIPO_TOPO_TOBs_unit    -- convert 6*32b Topo TOBs into one 192b word for Circular DPR
    Port map (                                                                                                 
        clk_in_280M              =>  clk_in_280M_i,                                                             
        TOBs_in                  =>  TOBs_32b_in,        -- 32b TOPO TOB                                   
        TOBs_sync_in             =>  TOBs_sync_in,                                                        
        TOB_valid_flg_in         =>  TOBs_valid_flg_in, 
        ALGO_TOB_BCN_in          =>  ALGO_TOB_BCN_in,  -- input from top                                     
        TOPO_TOB_out             =>  SIPO_T_TOB_out_i,      -- 6 * 32b TOPO TOBs           
        TOPO_TOB_sync_out        =>  SIPO_T_TOB_sync_out_i,     -- plus Sync signal
        TOPO_TOB_valid_out       =>  T_TOB_valid_out_i,          -- plus Valid signal
        ALGO_TOB_BCN_out         =>  ALGO_TOB_BCN_out_i
        );
 
    -- L1A needs to be delayed by 1 clk so correct value is store just prior to another L1A increments the counter
    -- 209b = 7b TOB_BCN + 0000 +6b valid +192b data
    DPR_T_TOBs_in_i <=  ALGO_TOB_BCN_out_i & "0000"  & T_TOB_valid_out_i & SIPO_T_TOB_out_i;
    SIPO_T_TOB_sync_vec_i(0)     <= SIPO_T_TOB_sync_out_i ;   -- active once every 7 clks
 
-- This state machine is responsible for reading 6 x 32-bit TOBs and 6 valid flags from Circular DPRAM,
-- and storing them into de-randomisation FIFO for the TOBs..
 
U3_TOBs_wr_FSM :  entity TOB_rdout_lib.fsm_TOB_wr_to_FIFO
    PORT map (
        CLK_IN                 => clk_in_280M_i ,
        TOB_FIFO_sw_rst        => TOB_FIFO_sw_rst,    -- RST OR TOB_FIFO_sw_rst
        L1A_in                 => L1A_in_i ,
        -- this is sync signal which enables WR addr to increase 
        -- can be either TOB_eg_sync_in or TOB_tau_sync_in as they are identical
        SIPO_sync_in           => TOBs_sync_in ,  
        pre_ld_wr_addr         => pre_ld_wr_addr_TOB ,        -- i/p
        DPR_locations_to_rd    => DPR_locations_to_rd ,   -- number of DRP locations to read 1 to 5
        trigger_slice_in       => trigger_slice_in,
        DPR_rd_addr            => DPR_T_TOB_rd_addr_i ,
        DPR_wr_addr            => DPR_T_TOB_wr_addr_i ,
        DRP_rd_en              => DRP_T_TOB_rd_en_i ,
        FIFO_wr_en             => FIFO_wr_en_i,
        tob_data_dpram_fsm     => tob_data_dpram_fsm
       );
       
-- This is Circular DPRAM for 192-bit sorted TOBs, 6-bit valid flags and 12-bit BCN
-- only 6 TOBs are written, 7th is ignored.
-- Each location of DPRAM stores all the TOBs for for one BCN.
 
U4_T_TOB_DRP : DPR_209b_512     -- Topo TOBs  into DPRAM
    PORT map (
        clka   => clk_in_280M_i,    -- runs at 280M but writes 1 in 7 clks
        ena    => tied_to_vcc_i  , 
        wea    => SIPO_T_TOB_sync_vec_i  ,   -- this is wr en using input sync sig
        addra  => DPR_T_TOB_wr_addr_i ,
        dina   => DPR_T_TOBs_in_i  ,         -- this is TOBs together 209b = 7b+4b+6b+192b TOB_BCN+ERR+valid+T_TOB
        clkb   => clk_in_280M_i  ,
        enb    => DRP_T_TOB_rd_en_i  ,       -- clk/rst/addr en for DPRAM port B
        addrb  => DPR_T_TOB_rd_addr_i  ,
        doutb  => DPR_T_TOBs_out_i           --  TOB out 209b = 7b+4b+6b+192b TOB_BCN+ERR+valid+T_TOB
        );
 
--U5_ila_T_TOBs_fifo : ila_ipbus_fabric_rd_wr
--PORT MAP (
--  clk    =>  clk_in_280M_i,     
--  probe0(8 downto 0) =>  DPR_T_TOB_wr_addr_i,       -- 36b    
--  probe0(15 downto 9) =>  (others => '0') ,       -- 36b    
--  probe0(24 downto 16) =>  DPR_T_TOB_rd_addr_i,       -- 36b    
--  probe0(35 downto 25) =>  (others => '0') ,       -- 36b    
--  probe1 =>  DPR_T_TOBs_in_i(208 downto 173),  -- 36b 
--  probe2(0) =>  DRP_T_TOB_rd_en_i ,   -- 1b 
--  probe3(0) =>  SIPO_T_TOB_sync_out_i,   -- 1b 
--  probe4(0) =>  L1A_in_i ,   -- 1b
--  probe5 =>  DPR_T_TOBs_out_i(208 downto 173),  -- 36b 
--  probe6 =>  DPR_T_TOBs_out_i(35 downto 0),        -- 36b
--  probe7(0) =>   FIFO_rd_en,             -- 1b
--  probe8(0) =>   FIFO_wr_en_tmp ,       -- 1b
--    probe9(0) =>   FIFO_wr_en_i              -- 1b
--);  
 
 
-- This is de-randomistion FIFO for 192-bit sorted TOBs, 4-bit errors, 6-bit valid flags and 7-bit BCN.
-- When an L1A arrives, the data associated with correct BCN is transferred from Circular DPRAM into de-randomistion FIFO.
-- 
U5_T_TOBs_fifo : FIFO_209b_512      -- Topo TOBs into FIFO on L1A
    PORT MAP (
        clk         => clk_in_280M_i,
        srst        => TOB_FIFO_sw_rst,         -- RST OR TOB_FIFO_sw_rst
        din         => DPR_T_TOBs_out_i ,       --  TOB out 209b = 7b+4b+6b+192b TOB_BCN+ERR+valid+T_TOB
        wr_en       => FIFO_wr_en_tmp,          -- stop wrtie if prog FULL is set
        rd_en       => FIFO_rd_en,
        dout        => rdout_T_TOB_209b_i  ,      --  TOB out 209b = 7b+4b+6b+192b TOB_BCN+ERR+valid+T_TOB
        data_count  => TOBs_FIFO_data_count_i,    -- TOBs FIFO occupancy count
        full        => TOBs_data_full_i,
        empty       => TOBs_data_empty_i,
        valid       => TOBs_data_valid_i,
        prog_full   => TOBs_data_prog_full_i,
        prog_full_thresh_assert     => TOBs_FIFO_pFULL_THRESH_assert,
        prog_full_thresh_negate     => TOBs_FIFO_pFULL_THRESH_negate
        );
    
end RTL;